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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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7042bde216
On resuming, we anticipate that the jack is detected before playback or capture. Therefore, we use semaphore to control the jack detection done without any bothering. During booting, the driver launches jack detection and releases the semaphore. However, it doesn't perceive the maniputation of semaphore is not like resuming procedure. This makes the semaphore's count value become to 2. There is more than one thread can enter into the critical section. This may get unexpected situation and make some chaos. Signed-off-by: SJLIN0 <SJLIN0@nuvoton.com> Signed-off-by: Wallace Lin <savagecin@gmail.com> Link: https://lore.kernel.org/r/20220915012800.825196-1-SJLIN0@nuvoton.com Signed-off-by: Mark Brown <broonie@kernel.org>
477 lines
16 KiB
C
477 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* NAU88L24 ALSA SoC audio driver
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*
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* Copyright 2016 Nuvoton Technology Corp.
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* Author: John Hsu <KCHSU0@nuvoton.com>
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*/
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#ifndef __NAU8824_H__
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#define __NAU8824_H__
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#define NAU8824_REG_RESET 0x00
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#define NAU8824_REG_ENA_CTRL 0x01
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#define NAU8824_REG_CLK_GATING_ENA 0x02
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#define NAU8824_REG_CLK_DIVIDER 0x03
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#define NAU8824_REG_FLL1 0x04
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#define NAU8824_REG_FLL2 0x05
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#define NAU8824_REG_FLL3 0x06
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#define NAU8824_REG_FLL4 0x07
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#define NAU8824_REG_FLL5 0x08
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#define NAU8824_REG_FLL6 0x09
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#define NAU8824_REG_FLL_VCO_RSV 0x0A
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#define NAU8824_REG_JACK_DET_CTRL 0x0D
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#define NAU8824_REG_INTERRUPT_SETTING_1 0x0F
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#define NAU8824_REG_IRQ 0x10
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#define NAU8824_REG_CLEAR_INT_REG 0x11
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#define NAU8824_REG_INTERRUPT_SETTING 0x12
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#define NAU8824_REG_SAR_ADC 0x13
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#define NAU8824_REG_VDET_COEFFICIENT 0x14
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#define NAU8824_REG_VDET_THRESHOLD_1 0x15
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#define NAU8824_REG_VDET_THRESHOLD_2 0x16
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#define NAU8824_REG_VDET_THRESHOLD_3 0x17
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#define NAU8824_REG_VDET_THRESHOLD_4 0x18
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#define NAU8824_REG_GPIO_SEL 0x1A
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#define NAU8824_REG_PORT0_I2S_PCM_CTRL_1 0x1C
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#define NAU8824_REG_PORT0_I2S_PCM_CTRL_2 0x1D
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#define NAU8824_REG_PORT0_LEFT_TIME_SLOT 0x1E
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#define NAU8824_REG_PORT0_RIGHT_TIME_SLOT 0x1F
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#define NAU8824_REG_TDM_CTRL 0x20
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#define NAU8824_REG_ADC_HPF_FILTER 0x23
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#define NAU8824_REG_ADC_FILTER_CTRL 0x24
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#define NAU8824_REG_DAC_FILTER_CTRL_1 0x25
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#define NAU8824_REG_DAC_FILTER_CTRL_2 0x26
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#define NAU8824_REG_NOTCH_FILTER_1 0x27
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#define NAU8824_REG_NOTCH_FILTER_2 0x28
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#define NAU8824_REG_EQ1_LOW 0x29
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#define NAU8824_REG_EQ2_EQ3 0x2A
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#define NAU8824_REG_EQ4_EQ5 0x2B
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#define NAU8824_REG_ADC_CH0_DGAIN_CTRL 0x2D
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#define NAU8824_REG_ADC_CH1_DGAIN_CTRL 0x2E
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#define NAU8824_REG_ADC_CH2_DGAIN_CTRL 0x2F
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#define NAU8824_REG_ADC_CH3_DGAIN_CTRL 0x30
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#define NAU8824_REG_DAC_MUTE_CTRL 0x31
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#define NAU8824_REG_DAC_CH0_DGAIN_CTRL 0x32
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#define NAU8824_REG_DAC_CH1_DGAIN_CTRL 0x33
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#define NAU8824_REG_ADC_TO_DAC_ST 0x34
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#define NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 0x38
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#define NAU8824_REG_DRC_KNEE_IP34_ADC_CH01 0x39
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#define NAU8824_REG_DRC_SLOPE_ADC_CH01 0x3A
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#define NAU8824_REG_DRC_ATKDCY_ADC_CH01 0x3B
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#define NAU8824_REG_DRC_KNEE_IP12_ADC_CH23 0x3C
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#define NAU8824_REG_DRC_KNEE_IP34_ADC_CH23 0x3D
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#define NAU8824_REG_DRC_SLOPE_ADC_CH23 0x3E
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#define NAU8824_REG_DRC_ATKDCY_ADC_CH23 0x3F
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#define NAU8824_REG_DRC_GAINL_ADC0 0x40
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#define NAU8824_REG_DRC_GAINL_ADC1 0x41
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#define NAU8824_REG_DRC_GAINL_ADC2 0x42
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#define NAU8824_REG_DRC_GAINL_ADC3 0x43
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#define NAU8824_REG_DRC_KNEE_IP12_DAC 0x45
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#define NAU8824_REG_DRC_KNEE_IP34_DAC 0x46
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#define NAU8824_REG_DRC_SLOPE_DAC 0x47
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#define NAU8824_REG_DRC_ATKDCY_DAC 0x48
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#define NAU8824_REG_DRC_GAIN_DAC_CH0 0x49
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#define NAU8824_REG_DRC_GAIN_DAC_CH1 0x4A
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#define NAU8824_REG_MODE 0x4C
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#define NAU8824_REG_MODE1 0x4D
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#define NAU8824_REG_MODE2 0x4E
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#define NAU8824_REG_CLASSG 0x50
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#define NAU8824_REG_OTP_EFUSE 0x51
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#define NAU8824_REG_OTPDOUT_1 0x53
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#define NAU8824_REG_OTPDOUT_2 0x54
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#define NAU8824_REG_MISC_CTRL 0x55
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#define NAU8824_REG_I2C_TIMEOUT 0x56
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#define NAU8824_REG_TEST_MODE 0x57
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#define NAU8824_REG_I2C_DEVICE_ID 0x58
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#define NAU8824_REG_SAR_ADC_DATA_OUT 0x59
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#define NAU8824_REG_BIAS_ADJ 0x66
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#define NAU8824_REG_PGA_GAIN 0x67
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#define NAU8824_REG_TRIM_SETTINGS 0x68
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#define NAU8824_REG_ANALOG_CONTROL_1 0x69
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#define NAU8824_REG_ANALOG_CONTROL_2 0x6A
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#define NAU8824_REG_ENABLE_LO 0x6B
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#define NAU8824_REG_GAIN_LO 0x6C
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#define NAU8824_REG_CLASSD_GAIN_1 0x6D
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#define NAU8824_REG_CLASSD_GAIN_2 0x6E
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#define NAU8824_REG_ANALOG_ADC_1 0x71
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#define NAU8824_REG_ANALOG_ADC_2 0x72
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#define NAU8824_REG_RDAC 0x73
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#define NAU8824_REG_MIC_BIAS 0x74
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#define NAU8824_REG_HS_VOLUME_CONTROL 0x75
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#define NAU8824_REG_BOOST 0x76
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#define NAU8824_REG_FEPGA 0x77
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#define NAU8824_REG_FEPGA_II 0x78
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#define NAU8824_REG_FEPGA_SE 0x79
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#define NAU8824_REG_FEPGA_ATTENUATION 0x7A
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#define NAU8824_REG_ATT_PORT0 0x7B
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#define NAU8824_REG_ATT_PORT1 0x7C
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#define NAU8824_REG_POWER_UP_CONTROL 0x7F
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#define NAU8824_REG_CHARGE_PUMP_CONTROL 0x80
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#define NAU8824_REG_CHARGE_PUMP_INPUT 0x81
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#define NAU8824_REG_MAX NAU8824_REG_CHARGE_PUMP_INPUT
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/* 16-bit control register address, and 16-bits control register data */
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#define NAU8824_REG_ADDR_LEN 16
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#define NAU8824_REG_DATA_LEN 16
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/* ENA_CTRL (0x1) */
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#define NAU8824_DMIC_LCH_EDGE_CH23 (0x1 << 12)
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#define NAU8824_DMIC_LCH_EDGE_CH01 (0x1 << 11)
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#define NAU8824_JD_SLEEP_MODE (0x1 << 10)
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#define NAU8824_ADC_CH3_DMIC_SFT 9
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#define NAU8824_ADC_CH3_DMIC_EN (0x1 << NAU8824_ADC_CH3_DMIC_SFT)
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#define NAU8824_ADC_CH2_DMIC_SFT 8
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#define NAU8824_ADC_CH2_DMIC_EN (0x1 << NAU8824_ADC_CH2_DMIC_SFT)
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#define NAU8824_ADC_CH1_DMIC_SFT 7
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#define NAU8824_ADC_CH1_DMIC_EN (0x1 << NAU8824_ADC_CH1_DMIC_SFT)
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#define NAU8824_ADC_CH0_DMIC_SFT 6
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#define NAU8824_ADC_CH0_DMIC_EN (0x1 << NAU8824_ADC_CH0_DMIC_SFT)
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#define NAU8824_DAC_CH1_EN (0x1 << 5)
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#define NAU8824_DAC_CH0_EN (0x1 << 4)
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#define NAU8824_ADC_CH3_EN (0x1 << 3)
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#define NAU8824_ADC_CH2_EN (0x1 << 2)
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#define NAU8824_ADC_CH1_EN (0x1 << 1)
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#define NAU8824_ADC_CH0_EN 0x1
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/* CLK_GATING_ENA (0x02) */
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#define NAU8824_CLK_ADC_CH23_EN (0x1 << 15)
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#define NAU8824_CLK_ADC_CH01_EN (0x1 << 14)
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#define NAU8824_CLK_DAC_CH1_EN (0x1 << 13)
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#define NAU8824_CLK_DAC_CH0_EN (0x1 << 12)
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#define NAU8824_CLK_I2S_EN (0x1 << 7)
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#define NAU8824_CLK_GAIN_EN (0x1 << 5)
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#define NAU8824_CLK_SAR_EN (0x1 << 3)
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#define NAU8824_CLK_DMIC_CH23_EN (0x1 << 1)
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/* CLK_DIVIDER (0x3) */
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#define NAU8824_CLK_SRC_SFT 15
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#define NAU8824_CLK_SRC_MASK (1 << NAU8824_CLK_SRC_SFT)
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#define NAU8824_CLK_SRC_VCO (1 << NAU8824_CLK_SRC_SFT)
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#define NAU8824_CLK_SRC_MCLK (0 << NAU8824_CLK_SRC_SFT)
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#define NAU8824_CLK_MCLK_SRC_MASK (0xf << 0)
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#define NAU8824_CLK_DMIC_SRC_SFT 10
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#define NAU8824_CLK_DMIC_SRC_MASK (0x7 << NAU8824_CLK_DMIC_SRC_SFT)
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#define NAU8824_CLK_ADC_SRC_SFT 6
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#define NAU8824_CLK_ADC_SRC_MASK (0x3 << NAU8824_CLK_ADC_SRC_SFT)
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#define NAU8824_CLK_DAC_SRC_SFT 4
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#define NAU8824_CLK_DAC_SRC_MASK (0x3 << NAU8824_CLK_DAC_SRC_SFT)
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/* FLL1 (0x04) */
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#define NAU8824_FLL_RATIO_MASK (0x7f << 0)
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/* FLL3 (0x06) */
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#define NAU8824_FLL_INTEGER_MASK (0x3ff << 0)
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#define NAU8824_FLL_CLK_SRC_SFT 10
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#define NAU8824_FLL_CLK_SRC_MASK (0x3 << NAU8824_FLL_CLK_SRC_SFT)
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#define NAU8824_FLL_CLK_SRC_MCLK (0 << NAU8824_FLL_CLK_SRC_SFT)
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#define NAU8824_FLL_CLK_SRC_BLK (0x2 << NAU8824_FLL_CLK_SRC_SFT)
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#define NAU8824_FLL_CLK_SRC_FS (0x3 << NAU8824_FLL_CLK_SRC_SFT)
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/* FLL4 (0x07) */
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#define NAU8824_FLL_REF_DIV_SFT 10
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#define NAU8824_FLL_REF_DIV_MASK (0x3 << NAU8824_FLL_REF_DIV_SFT)
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/* FLL5 (0x08) */
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#define NAU8824_FLL_PDB_DAC_EN (0x1 << 15)
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#define NAU8824_FLL_LOOP_FTR_EN (0x1 << 14)
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#define NAU8824_FLL_CLK_SW_MASK (0x1 << 13)
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#define NAU8824_FLL_CLK_SW_N2 (0x1 << 13)
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#define NAU8824_FLL_CLK_SW_REF (0x0 << 13)
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#define NAU8824_FLL_FTR_SW_MASK (0x1 << 12)
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#define NAU8824_FLL_FTR_SW_ACCU (0x1 << 12)
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#define NAU8824_FLL_FTR_SW_FILTER (0x0 << 12)
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/* FLL6 (0x9) */
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#define NAU8824_DCO_EN (0x1 << 15)
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#define NAU8824_SDM_EN (0x1 << 14)
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/* IRQ (0x10) */
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#define NAU8824_SHORT_CIRCUIT_IRQ (0x1 << 7)
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#define NAU8824_IMPEDANCE_MEAS_IRQ (0x1 << 6)
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#define NAU8824_KEY_RELEASE_IRQ (0x1 << 5)
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#define NAU8824_KEY_LONG_PRESS_IRQ (0x1 << 4)
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#define NAU8824_KEY_SHORT_PRESS_IRQ (0x1 << 3)
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#define NAU8824_JACK_EJECTION_DETECTED (0x1 << 1)
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#define NAU8824_JACK_INSERTION_DETECTED 0x1
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/* JACK_DET_CTRL (0x0D) */
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#define NAU8824_JACK_EJECT_DT_SFT 2
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#define NAU8824_JACK_EJECT_DT_MASK (0x3 << NAU8824_JACK_EJECT_DT_SFT)
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#define NAU8824_JACK_LOGIC (0x1 << 1)
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/* INTERRUPT_SETTING_1 (0x0F) */
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#define NAU8824_IRQ_EJECT_EN (0x1 << 9)
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#define NAU8824_IRQ_INSERT_EN (0x1 << 8)
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/* INTERRUPT_SETTING (0x12) */
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#define NAU8824_IRQ_KEY_RELEASE_DIS (0x1 << 5)
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#define NAU8824_IRQ_KEY_SHORT_PRESS_DIS (0x1 << 3)
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#define NAU8824_IRQ_EJECT_DIS (0x1 << 1)
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#define NAU8824_IRQ_INSERT_DIS 0x1
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/* SAR_ADC (0x13) */
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#define NAU8824_SAR_ADC_EN_SFT 12
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#define NAU8824_SAR_TRACKING_GAIN_SFT 8
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#define NAU8824_SAR_TRACKING_GAIN_MASK (0x7 << NAU8824_SAR_TRACKING_GAIN_SFT)
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#define NAU8824_SAR_COMPARE_TIME_SFT 2
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#define NAU8824_SAR_COMPARE_TIME_MASK (3 << 2)
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#define NAU8824_SAR_SAMPLING_TIME_SFT 0
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#define NAU8824_SAR_SAMPLING_TIME_MASK (3 << 0)
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/* VDET_COEFFICIENT (0x14) */
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#define NAU8824_SHORTKEY_DEBOUNCE_SFT 12
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#define NAU8824_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8824_SHORTKEY_DEBOUNCE_SFT)
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#define NAU8824_LEVELS_NR_SFT 8
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#define NAU8824_LEVELS_NR_MASK (0x7 << 8)
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#define NAU8824_HYSTERESIS_SFT 0
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#define NAU8824_HYSTERESIS_MASK 0xf
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/* PORT0_I2S_PCM_CTRL_1 (0x1C) */
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#define NAU8824_I2S_BP_SFT 7
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#define NAU8824_I2S_BP_MASK (1 << NAU8824_I2S_BP_SFT)
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#define NAU8824_I2S_BP_INV (1 << NAU8824_I2S_BP_SFT)
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#define NAU8824_I2S_PCMB_SFT 6
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#define NAU8824_I2S_PCMB_EN (1 << NAU8824_I2S_PCMB_SFT)
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#define NAU8824_I2S_DL_SFT 2
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#define NAU8824_I2S_DL_MASK (0x3 << NAU8824_I2S_DL_SFT)
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#define NAU8824_I2S_DL_16 (0 << NAU8824_I2S_DL_SFT)
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#define NAU8824_I2S_DL_20 (1 << NAU8824_I2S_DL_SFT)
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#define NAU8824_I2S_DL_24 (2 << NAU8824_I2S_DL_SFT)
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#define NAU8824_I2S_DL_32 (3 << NAU8824_I2S_DL_SFT)
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#define NAU8824_I2S_DF_MASK 0x3
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#define NAU8824_I2S_DF_RIGTH 0
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#define NAU8824_I2S_DF_LEFT 1
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#define NAU8824_I2S_DF_I2S 2
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#define NAU8824_I2S_DF_PCM_AB 3
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/* PORT0_I2S_PCM_CTRL_2 (0x1D) */
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#define NAU8824_I2S_LRC_DIV_SFT 12
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#define NAU8824_I2S_LRC_DIV_MASK (0x3 << NAU8824_I2S_LRC_DIV_SFT)
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#define NAU8824_I2S_MS_SFT 3
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#define NAU8824_I2S_MS_MASK (1 << NAU8824_I2S_MS_SFT)
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#define NAU8824_I2S_MS_MASTER (1 << NAU8824_I2S_MS_SFT)
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#define NAU8824_I2S_MS_SLAVE (0 << NAU8824_I2S_MS_SFT)
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#define NAU8824_I2S_BLK_DIV_MASK 0x7
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/* PORT0_LEFT_TIME_SLOT (0x1E) */
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#define NAU8824_TSLOT_L_MASK 0x3ff
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/* TDM_CTRL (0x20) */
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#define NAU8824_TDM_MODE (0x1 << 15)
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#define NAU8824_TDM_OFFSET_EN (0x1 << 14)
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#define NAU8824_TDM_DACL_RX_SFT 6
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#define NAU8824_TDM_DACL_RX_MASK (0x3 << NAU8824_TDM_DACL_RX_SFT)
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#define NAU8824_TDM_DACR_RX_SFT 4
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#define NAU8824_TDM_DACR_RX_MASK (0x3 << NAU8824_TDM_DACR_RX_SFT)
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#define NAU8824_TDM_TX_MASK 0xf
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/* ADC_FILTER_CTRL (0x24) */
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#define NAU8824_ADC_SYNC_DOWN_MASK 0x3
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#define NAU8824_ADC_SYNC_DOWN_32 0
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#define NAU8824_ADC_SYNC_DOWN_64 1
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#define NAU8824_ADC_SYNC_DOWN_128 2
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#define NAU8824_ADC_SYNC_DOWN_256 3
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/* DAC_FILTER_CTRL_1 (0x25) */
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#define NAU8824_DAC_CICCLP_OFF (0x1 << 7)
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#define NAU8824_DAC_OVERSAMPLE_MASK 0x7
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#define NAU8824_DAC_OVERSAMPLE_64 0
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#define NAU8824_DAC_OVERSAMPLE_256 1
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#define NAU8824_DAC_OVERSAMPLE_128 2
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#define NAU8824_DAC_OVERSAMPLE_32 4
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/* DAC_MUTE_CTRL (0x31) */
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#define NAU8824_DAC_CH01_MIX 0x3
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#define NAU8824_DAC_ZC_EN (0x1 << 11)
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/* DAC_CH0_DGAIN_CTRL (0x32) */
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#define NAU8824_DAC_CH0_SEL_SFT 9
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#define NAU8824_DAC_CH0_SEL_MASK (0x1 << NAU8824_DAC_CH0_SEL_SFT)
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#define NAU8824_DAC_CH0_SEL_I2S0 (0x0 << NAU8824_DAC_CH0_SEL_SFT)
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#define NAU8824_DAC_CH0_SEL_I2S1 (0x1 << NAU8824_DAC_CH0_SEL_SFT)
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#define NAU8824_DAC_CH0_VOL_MASK 0x1ff
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/* DAC_CH1_DGAIN_CTRL (0x33) */
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#define NAU8824_DAC_CH1_SEL_SFT 9
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#define NAU8824_DAC_CH1_SEL_MASK (0x1 << NAU8824_DAC_CH1_SEL_SFT)
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#define NAU8824_DAC_CH1_SEL_I2S0 (0x0 << NAU8824_DAC_CH1_SEL_SFT)
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#define NAU8824_DAC_CH1_SEL_I2S1 (0x1 << NAU8824_DAC_CH1_SEL_SFT)
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#define NAU8824_DAC_CH1_VOL_MASK 0x1ff
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/* CLASSG (0x50) */
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#define NAU8824_CLASSG_TIMER_SFT 8
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#define NAU8824_CLASSG_TIMER_MASK (0x3f << NAU8824_CLASSG_TIMER_SFT)
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#define NAU8824_CLASSG_LDAC_EN_SFT 2
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#define NAU8824_CLASSG_RDAC_EN_SFT 1
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#define NAU8824_CLASSG_EN_SFT 0
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/* SAR_ADC_DATA_OUT (0x59) */
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#define NAU8824_SAR_ADC_DATA_MASK 0xff
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/* BIAS_ADJ (0x66) */
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#define NAU8824_VMID (1 << 6)
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#define NAU8824_VMID_SEL_SFT 4
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#define NAU8824_VMID_SEL_MASK (3 << NAU8824_VMID_SEL_SFT)
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#define NAU8824_DMIC2_EN_SFT 3
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#define NAU8824_DMIC1_EN_SFT 2
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/* TRIM_SETTINGS (0x68) */
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#define NAU8824_DRV_CURR_INC (1 << 15)
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/* ANALOG_CONTROL_1 (0x69) */
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#define NAU8824_DMIC_CLK_DRV_STRG (1 << 3)
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#define NAU8824_DMIC_CLK_SLEW_FAST (0x7)
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/* ANALOG_CONTROL_2 (0x6A) */
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#define NAU8824_CLASSD_CLAMP_DIS_SFT 3
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#define NAU8824_CLASSD_CLAMP_DIS (0x1 << NAU8824_CLASSD_CLAMP_DIS_SFT)
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/* ENABLE_LO (0x6B) */
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#define NAU8824_TEST_DAC_SFT 14
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#define NAU8824_TEST_DAC_EN (0x3 << NAU8824_TEST_DAC_SFT)
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#define NAU8824_DACL_HPR_EN_SFT 3
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#define NAU8824_DACL_HPR_EN (0x1 << NAU8824_DACL_HPR_EN_SFT)
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#define NAU8824_DACR_HPR_EN_SFT 2
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#define NAU8824_DACR_HPR_EN (0x1 << NAU8824_DACR_HPR_EN_SFT)
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#define NAU8824_DACR_HPL_EN_SFT 1
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#define NAU8824_DACR_HPL_EN (0x1 << NAU8824_DACR_HPL_EN_SFT)
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#define NAU8824_DACL_HPL_EN_SFT 0
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#define NAU8824_DACL_HPL_EN 0x1
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/* CLASSD_GAIN_1 (0x6D) */
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#define NAU8824_CLASSD_GAIN_1R_SFT 8
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#define NAU8824_CLASSD_GAIN_1R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
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#define NAU8824_CLASSD_EN_SFT 7
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#define NAU8824_CLASSD_EN (0x1 << NAU8824_CLASSD_EN_SFT)
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#define NAU8824_CLASSD_GAIN_1L_MASK 0x1f
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/* CLASSD_GAIN_2 (0x6E) */
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#define NAU8824_CLASSD_GAIN_2R_SFT 8
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#define NAU8824_CLASSD_GAIN_2R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
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#define NAU8824_CLASSD_EN_SFT 7
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#define NAU8824_CLASSD_EN (0x1 << NAU8824_CLASSD_EN_SFT)
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#define NAU8824_CLASSD_GAIN_2L_MASK 0x1f
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/* ANALOG_ADC_2 (0x72) */
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#define NAU8824_ADCR_EN_SFT 7
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#define NAU8824_ADCL_EN_SFT 6
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/* RDAC (0x73) */
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#define NAU8824_DACR_EN_SFT 13
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#define NAU8824_DACL_EN_SFT 12
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#define NAU8824_DACR_CLK_SFT 9
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#define NAU8824_DACL_CLK_SFT 8
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#define NAU8824_RDAC_CLK_DELAY_SFT 4
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#define NAU8824_RDAC_CLK_DELAY_MASK (0x7 << NAU8824_RDAC_CLK_DELAY_SFT)
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#define NAU8824_RDAC_VREF_SFT 2
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#define NAU8824_RDAC_VREF_MASK (0x3 << NAU8824_RDAC_VREF_SFT)
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/* MIC_BIAS (0x74) */
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#define NAU8824_MICBIAS_JKSLV (1 << 14)
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#define NAU8824_MICBIAS_JKR2 (1 << 12)
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#define NAU8824_MICBIAS_POWERUP_SFT 8
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#define NAU8824_MICBIAS_VOLTAGE_SFT 0
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#define NAU8824_MICBIAS_VOLTAGE_MASK 0x7
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/* BOOST (0x76) */
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#define NAU8824_PRECHARGE_DIS (0x1 << 13)
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#define NAU8824_GLOBAL_BIAS_EN (0x1 << 12)
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#define NAU8824_HP_BOOST_DIS_SFT 9
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#define NAU8824_HP_BOOST_DIS (0x1 << NAU8824_HP_BOOST_DIS_SFT)
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#define NAU8824_HP_BOOST_G_DIS_SFT 8
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#define NAU8824_HP_BOOST_G_DIS (0x1 << NAU8824_HP_BOOST_G_DIS_SFT)
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#define NAU8824_SHORT_SHUTDOWN_DIG_EN (1 << 7)
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#define NAU8824_SHORT_SHUTDOWN_EN (1 << 6)
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/* FEPGA (0x77) */
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#define NAU8824_FEPGA_MODER_SHORT_SFT 7
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#define NAU8824_FEPGA_MODER_SHORT_EN (0x1 << NAU8824_FEPGA_MODER_SHORT_SFT)
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#define NAU8824_FEPGA_MODER_MIC2_SFT 5
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#define NAU8824_FEPGA_MODER_MIC2_EN (0x1 << NAU8824_FEPGA_MODER_MIC2_SFT)
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#define NAU8824_FEPGA_MODER_HSMIC_SFT 4
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#define NAU8824_FEPGA_MODER_HSMIC_EN (0x1 << NAU8824_FEPGA_MODER_HSMIC_SFT)
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#define NAU8824_FEPGA_MODEL_SHORT_SFT 3
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#define NAU8824_FEPGA_MODEL_SHORT_EN (0x1 << NAU8824_FEPGA_MODEL_SHORT_SFT)
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#define NAU8824_FEPGA_MODEL_MIC1_SFT 1
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#define NAU8824_FEPGA_MODEL_MIC1_EN (0x1 << NAU8824_FEPGA_MODEL_MIC1_SFT)
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#define NAU8824_FEPGA_MODEL_HSMIC_SFT 0
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#define NAU8824_FEPGA_MODEL_HSMIC_EN (0x1 << NAU8824_FEPGA_MODEL_HSMIC_SFT)
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/* FEPGA_II (0x78) */
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#define NAU8824_FEPGA_GAINR_SFT 5
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#define NAU8824_FEPGA_GAINR_MASK (0x1f << NAU8824_FEPGA_GAINR_SFT)
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#define NAU8824_FEPGA_GAINL_SFT 0
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#define NAU8824_FEPGA_GAINL_MASK 0x1f
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/* CHARGE_PUMP_CONTROL (0x80) */
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#define NAU8824_JAMNODCLOW (0x1 << 15)
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#define NAU8824_SPKR_PULL_DOWN (0x1 << 13)
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#define NAU8824_SPKL_PULL_DOWN (0x1 << 12)
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#define NAU8824_POWER_DOWN_DACR (0x1 << 9)
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#define NAU8824_POWER_DOWN_DACL (0x1 << 8)
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#define NAU8824_CHARGE_PUMP_EN_SFT 5
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#define NAU8824_CHARGE_PUMP_EN (0x1 << NAU8824_CHARGE_PUMP_EN_SFT)
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#define NAU8824_CODEC_DAI "nau8824-hifi"
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/* System Clock Source */
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enum {
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NAU8824_CLK_DIS,
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NAU8824_CLK_MCLK,
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NAU8824_CLK_INTERNAL,
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NAU8824_CLK_FLL_MCLK,
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NAU8824_CLK_FLL_BLK,
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NAU8824_CLK_FLL_FS,
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};
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struct nau8824 {
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struct device *dev;
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struct regmap *regmap;
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struct snd_soc_dapm_context *dapm;
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struct snd_soc_jack *jack;
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|
struct work_struct jdet_work;
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struct semaphore jd_sem;
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|
int fs;
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int irq;
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|
int resume_lock;
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|
int micbias_voltage;
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|
int vref_impedance;
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|
int jkdet_polarity;
|
|
int sar_threshold_num;
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|
int sar_threshold[8];
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|
int sar_hysteresis;
|
|
int sar_voltage;
|
|
int sar_compare_time;
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|
int sar_sampling_time;
|
|
int key_debounce;
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|
int jack_eject_debounce;
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|
};
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|
|
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struct nau8824_fll {
|
|
int mclk_src;
|
|
int ratio;
|
|
int fll_frac;
|
|
int fll_int;
|
|
int clk_ref_div;
|
|
};
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|
|
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struct nau8824_fll_attr {
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|
unsigned int param;
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|
unsigned int val;
|
|
};
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|
|
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struct nau8824_osr_attr {
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|
unsigned int osr;
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unsigned int clk_src;
|
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};
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int nau8824_enable_jack_detect(struct snd_soc_component *component,
|
|
struct snd_soc_jack *jack);
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const char *nau8824_components(void);
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#endif /* _NAU8824_H */
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