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![Johannes Berg](/assets/img/avatar_default.png)
The ICT code erroneously uses PAGE_SIZE. The bug is that PAGE_SIZE isn't necessarily 4096, so on such platforms this code will not work correctly as we'll try to attempt to read an index in the table that the device never wrote, it always has 4096-byte pages. Additionally, the manual alignment code here is unnecessary -- Documentation/DMA-API-HOWTO.txt states: The cpu return address and the DMA bus master address are both guaranteed to be aligned to the smallest PAGE_SIZE order which is greater than or equal to the requested size. This invariant exists (for example) to guarantee that if you allocate a chunk which is smaller than or equal to 64 kilobytes, the extent of the buffer you receive will not cross a 64K boundary. Just use appropriate new constants and get rid of the alignment code. Cc: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
459 lines
14 KiB
C
459 lines
14 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
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*
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* Portions of this file are derived from the ipw3945 project, as well
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* as portions of the ieee80211 subsystem header files.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#ifndef __iwl_trans_int_pcie_h__
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#define __iwl_trans_int_pcie_h__
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/skbuff.h>
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#include <linux/pci.h>
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#include "iwl-fh.h"
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#include "iwl-csr.h"
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#include "iwl-shared.h"
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#include "iwl-trans.h"
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#include "iwl-debug.h"
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#include "iwl-io.h"
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struct iwl_tx_queue;
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struct iwl_queue;
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struct iwl_host_cmd;
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/*This file includes the declaration that are internal to the
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* trans_pcie layer */
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/**
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* struct isr_statistics - interrupt statistics
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*
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*/
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struct isr_statistics {
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u32 hw;
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u32 sw;
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u32 err_code;
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u32 sch;
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u32 alive;
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u32 rfkill;
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u32 ctkill;
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u32 wakeup;
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u32 rx;
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u32 tx;
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u32 unhandled;
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};
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/**
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* struct iwl_rx_queue - Rx queue
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* @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
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* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
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* @pool:
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* @queue:
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* @read: Shared index to newest available Rx buffer
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* @write: Shared index to oldest written Rx packet
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* @free_count: Number of pre-allocated buffers in rx_free
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* @write_actual:
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* @rx_free: list of free SKBs for use
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* @rx_used: List of Rx buffers with no SKB
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* @need_update: flag to indicate we need to update read/write index
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* @rb_stts: driver's pointer to receive buffer status
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* @rb_stts_dma: bus address of receive buffer status
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* @lock:
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*
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* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
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*/
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struct iwl_rx_queue {
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__le32 *bd;
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dma_addr_t bd_dma;
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struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
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struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
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u32 read;
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u32 write;
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u32 free_count;
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u32 write_actual;
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struct list_head rx_free;
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struct list_head rx_used;
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int need_update;
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struct iwl_rb_status *rb_stts;
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dma_addr_t rb_stts_dma;
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spinlock_t lock;
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};
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struct iwl_dma_ptr {
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dma_addr_t dma;
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void *addr;
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size_t size;
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};
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/*
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* This queue number is required for proper operation
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* because the ucode will stop/start the scheduler as
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* required.
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*/
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#define IWL_IPAN_MCAST_QUEUE 8
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struct iwl_cmd_meta {
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/* only for SYNC commands, iff the reply skb is wanted */
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struct iwl_host_cmd *source;
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u32 flags;
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DEFINE_DMA_UNMAP_ADDR(mapping);
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DEFINE_DMA_UNMAP_LEN(len);
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};
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/*
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* Generic queue structure
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*
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* Contains common data for Rx and Tx queues.
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*
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* Note the difference between n_bd and n_window: the hardware
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* always assumes 256 descriptors, so n_bd is always 256 (unless
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* there might be HW changes in the future). For the normal TX
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* queues, n_window, which is the size of the software queue data
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* is also 256; however, for the command queue, n_window is only
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* 32 since we don't need so many commands pending. Since the HW
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* still uses 256 BDs for DMA though, n_bd stays 256. As a result,
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* the software buffers (in the variables @meta, @txb in struct
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* iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
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* in the same struct) have 256.
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* This means that we end up with the following:
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* HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
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* SW entries: | 0 | ... | 31 |
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* where N is a number between 0 and 7. This means that the SW
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* data is a window overlayed over the HW queue.
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*/
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struct iwl_queue {
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int n_bd; /* number of BDs in this queue */
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int write_ptr; /* 1-st empty entry (index) host_w*/
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int read_ptr; /* last used entry (index) host_r*/
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/* use for monitoring and recovering the stuck queue */
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dma_addr_t dma_addr; /* physical addr for BD's */
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int n_window; /* safe queue window */
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u32 id;
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int low_mark; /* low watermark, resume queue if free
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* space more than this */
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int high_mark; /* high watermark, stop queue if free
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* space less than this */
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};
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/**
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* struct iwl_tx_queue - Tx Queue for DMA
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* @q: generic Rx/Tx queue descriptor
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* @bd: base of circular buffer of TFDs
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* @cmd: array of command/TX buffer pointers
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* @meta: array of meta data for each command/tx buffer
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* @dma_addr_cmd: physical address of cmd/tx buffer array
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* @txb: array of per-TFD driver data
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* @time_stamp: time (in jiffies) of last read_ptr change
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* @need_update: indicates need to update read/write index
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* @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
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* @sta_id: valid if sched_retry is set
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* @tid: valid if sched_retry is set
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*
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* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
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* descriptors) and required locking structures.
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*/
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#define TFD_TX_CMD_SLOTS 256
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#define TFD_CMD_SLOTS 32
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struct iwl_tx_queue {
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struct iwl_queue q;
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struct iwl_tfd *tfds;
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struct iwl_device_cmd **cmd;
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struct iwl_cmd_meta *meta;
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struct sk_buff **skbs;
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unsigned long time_stamp;
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u8 need_update;
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u8 sched_retry;
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u8 active;
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u8 swq_id;
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u16 sta_id;
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u16 tid;
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};
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/**
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* struct iwl_trans_pcie - PCIe transport specific data
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* @rxq: all the RX queue data
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* @rx_replenish: work that will be called when buffers need to be allocated
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* @trans: pointer to the generic transport area
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* @scd_base_addr: scheduler sram base address in SRAM
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* @scd_bc_tbls: pointer to the byte count table of the scheduler
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* @kw: keep warm address
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* @ac_to_fifo: to what fifo is a specifc AC mapped ?
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* @ac_to_queue: to what tx queue is a specifc AC mapped ?
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* @mcast_queue:
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* @txq: Tx DMA processing queues
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* @txq_ctx_active_msk: what queue is active
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* queue_stopped: tracks what queue is stopped
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* queue_stop_count: tracks what SW queue is stopped
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*/
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struct iwl_trans_pcie {
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struct iwl_rx_queue rxq;
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struct work_struct rx_replenish;
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struct iwl_trans *trans;
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/* INT ICT Table */
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__le32 *ict_tbl;
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dma_addr_t ict_tbl_dma;
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int ict_index;
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u32 inta;
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bool use_ict;
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struct tasklet_struct irq_tasklet;
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struct isr_statistics isr_stats;
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u32 inta_mask;
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u32 scd_base_addr;
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struct iwl_dma_ptr scd_bc_tbls;
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struct iwl_dma_ptr kw;
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const u8 *ac_to_fifo[NUM_IWL_RXON_CTX];
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const u8 *ac_to_queue[NUM_IWL_RXON_CTX];
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u8 mcast_queue[NUM_IWL_RXON_CTX];
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u8 agg_txq[IWLAGN_STATION_COUNT][IWL_MAX_TID_COUNT];
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struct iwl_tx_queue *txq;
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unsigned long txq_ctx_active_msk;
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#define IWL_MAX_HW_QUEUES 32
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unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
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atomic_t queue_stop_count[4];
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};
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#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
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((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
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/*****************************************************
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* RX
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******************************************************/
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void iwl_bg_rx_replenish(struct work_struct *data);
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void iwl_irq_tasklet(struct iwl_trans *trans);
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void iwlagn_rx_replenish(struct iwl_trans *trans);
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void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
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struct iwl_rx_queue *q);
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/*****************************************************
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* ICT
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******************************************************/
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int iwl_reset_ict(struct iwl_trans *trans);
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void iwl_disable_ict(struct iwl_trans *trans);
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int iwl_alloc_isr_ict(struct iwl_trans *trans);
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void iwl_free_isr_ict(struct iwl_trans *trans);
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irqreturn_t iwl_isr_ict(int irq, void *data);
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/*****************************************************
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* TX / HCMD
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******************************************************/
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void iwl_txq_update_write_ptr(struct iwl_trans *trans,
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struct iwl_tx_queue *txq);
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int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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dma_addr_t addr, u16 len, u8 reset);
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int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
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int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
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void iwl_tx_cmd_complete(struct iwl_trans *trans,
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struct iwl_rx_mem_buffer *rxb, int handler_status);
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void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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u16 byte_cnt);
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int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
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int sta_id, int tid);
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void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
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void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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int tx_fifo_id, int scd_retry);
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int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, int sta_id, int tid);
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void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
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enum iwl_rxon_context_id ctx,
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int sta_id, int tid, int frame_limit, u16 ssn);
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void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
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int index, enum dma_data_direction dma_dir);
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int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
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struct sk_buff_head *skbs);
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int iwl_queue_space(const struct iwl_queue *q);
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/*****************************************************
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* Error handling
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******************************************************/
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int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
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char **buf, bool display);
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int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
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void iwl_dump_csr(struct iwl_trans *trans);
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/*****************************************************
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* Helpers
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******************************************************/
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static inline void iwl_disable_interrupts(struct iwl_trans *trans)
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{
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clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
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/* disable interrupts from uCode/NIC to host */
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iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
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/* acknowledge/clear/reset any interrupts still pending
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* from uCode or flow handler (Rx/Tx DMA) */
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iwl_write32(bus(trans), CSR_INT, 0xffffffff);
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iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
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IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
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}
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static inline void iwl_enable_interrupts(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
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set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
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iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
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}
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/*
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* we have 8 bits used like this:
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*
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* 7 6 5 4 3 2 1 0
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* | | | | | | | |
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* | | | | | | +-+-------- AC queue (0-3)
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* | | | | | |
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* | +-+-+-+-+------------ HW queue ID
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* |
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* +---------------------- unused
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*/
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static inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq)
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{
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BUG_ON(ac > 3); /* only have 2 bits */
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BUG_ON(hwq > 31); /* only use 5 bits */
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txq->swq_id = (hwq << 2) | ac;
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}
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static inline u8 iwl_get_queue_ac(struct iwl_tx_queue *txq)
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{
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return txq->swq_id & 0x3;
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}
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static inline void iwl_wake_queue(struct iwl_trans *trans,
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struct iwl_tx_queue *txq, const char *msg)
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{
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u8 queue = txq->swq_id;
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u8 ac = queue & 3;
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u8 hwq = (queue >> 2) & 0x1f;
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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if (test_and_clear_bit(hwq, trans_pcie->queue_stopped)) {
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if (atomic_dec_return(&trans_pcie->queue_stop_count[ac]) <= 0) {
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iwl_wake_sw_queue(priv(trans), ac);
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IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d ac %d. %s",
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hwq, ac, msg);
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} else {
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IWL_DEBUG_TX_QUEUES(trans, "Don't wake hwq %d ac %d"
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" stop count %d. %s",
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hwq, ac, atomic_read(&trans_pcie->
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queue_stop_count[ac]), msg);
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}
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}
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}
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static inline void iwl_stop_queue(struct iwl_trans *trans,
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struct iwl_tx_queue *txq, const char *msg)
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{
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u8 queue = txq->swq_id;
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u8 ac = queue & 3;
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u8 hwq = (queue >> 2) & 0x1f;
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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if (!test_and_set_bit(hwq, trans_pcie->queue_stopped)) {
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if (atomic_inc_return(&trans_pcie->queue_stop_count[ac]) > 0) {
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iwl_stop_sw_queue(priv(trans), ac);
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IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d ac %d"
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" stop count %d. %s",
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hwq, ac, atomic_read(&trans_pcie->
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queue_stop_count[ac]), msg);
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} else {
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IWL_DEBUG_TX_QUEUES(trans, "Don't stop hwq %d ac %d"
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" stop count %d. %s",
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hwq, ac, atomic_read(&trans_pcie->
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queue_stop_count[ac]), msg);
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}
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} else {
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IWL_DEBUG_TX_QUEUES(trans, "stop hwq %d, but it is stopped/ %s",
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hwq, msg);
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}
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}
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#ifdef ieee80211_stop_queue
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#undef ieee80211_stop_queue
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#endif
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#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
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#ifdef ieee80211_wake_queue
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#undef ieee80211_wake_queue
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#endif
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#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
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static inline void iwl_txq_ctx_activate(struct iwl_trans_pcie *trans_pcie,
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int txq_id)
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{
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set_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
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}
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static inline void iwl_txq_ctx_deactivate(struct iwl_trans_pcie *trans_pcie,
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int txq_id)
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{
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clear_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
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}
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static inline int iwl_queue_used(const struct iwl_queue *q, int i)
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{
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return q->write_ptr >= q->read_ptr ?
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(i >= q->read_ptr && i < q->write_ptr) :
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!(i < q->read_ptr && i >= q->write_ptr);
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}
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static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
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{
|
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return index & (q->n_window - 1);
|
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}
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|
|
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#define IWL_TX_FIFO_BK 0 /* shared */
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|
#define IWL_TX_FIFO_BE 1
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#define IWL_TX_FIFO_VI 2 /* shared */
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|
#define IWL_TX_FIFO_VO 3
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#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
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|
#define IWL_TX_FIFO_BE_IPAN 4
|
|
#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
|
|
#define IWL_TX_FIFO_VO_IPAN 5
|
|
/* re-uses the VO FIFO, uCode will properly flush/schedule */
|
|
#define IWL_TX_FIFO_AUX 5
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|
#define IWL_TX_FIFO_UNUSED -1
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|
|
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/* AUX (TX during scan dwell) queue */
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#define IWL_AUX_QUEUE 10
|
|
|
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#endif /* __iwl_trans_int_pcie_h__ */
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