Shawn Guo 4f71612ee3 ARM: imx: fix vf610 enet module clock selection ... The fec/enet driver calculates MDC rate with the formula below. ref_freq / ((MII_SPEED + 1) x 2) The ref_freq here is the fec internal module clock, which is missing from clk-vf610 clock driver right now. And clk-vf610 driver mistakenly supplies RMII clock (50 MHz) as the source to fec. This results in the situation that fec driver gets ref_freq as 50 MHz, while physically it runs at 66 MHz (fec module clock physically sources from ipg which runs at 66 MHz). That's why software expects MDC runs at 2.5 MHz, while the measurement tells it runs at 3.3 MHz. And this causes the PHY KSZ8041 keeps swithing between Full and Half mode as below. libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half Add the missing module clock for ENET0 and ENET1, and correct the clock supplying in device tree to fix above issue. Thanks to Alison Wang <b18965@freescale.com> for debugging the issue. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>		2013-07-15 08:28:09 +08:00
..
clk	clk: samsung: register audio subsystem clocks using common clock framework	2013-06-19 03:28:41 +09:00
clock	ARM: imx: fix vf610 enet module clock selection	2013-07-15 08:28:09 +08:00
dma	ARM: at91: dt: add header to define at_hdmac configuration	2013-06-15 00:12:30 +02:00
gpio	ARM: tegra: create a DT header defining GPIO IDs	2013-05-28 16:13:49 -06:00
interrupt-controller	ARM: dt: create a DT header for the GIC	2013-04-05 12:23:24 -06:00
pinctrl	Pin control changes for the v3.11 kernel cycle:	2013-07-03 11:48:03 -07:00