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The GIC architecture specification defines a set of registers for redistributors and ITSes that control the sharebility and cacheability attributes of redistributors/ITSes initiator ports on the interconnect (GICR_[V]PROPBASER, GICR_[V]PENDBASER, GITS_BASER<n>). Architecturally the GIC provides a means to drive shareability and cacheability attributes signals and related IWB/OWB/ISH barriers but it is not mandatory for designs to wire up the corresponding interconnect signals that control the cacheability/shareability of transactions. Redistributors and ITSes interconnect ports can be connected to non-coherent interconnects that are not able to manage the shareability/cacheability attributes; this implicitly makes the redistributors and ITSes non-coherent observers. So far, the GIC driver on probe executes a write to "probe" for the redistributors and ITSes registers shareability bitfields by writing a value (ie InnerShareable - the shareability domain the CPUs are in) and check it back to detect whether the value sticks or not; this hinges on a GIC programming model behaviour that predates the current specifications, that just define shareability bits as writeable but do not guarantee that writing certain shareability values enable the expected behaviour for the redistributors/ITSes memory interconnect ports. To enable non-coherent GIC designs, introduce the "dma-noncoherent" device tree property to allow firmware to describe redistributors and ITSes as non-coherent observers on the memory interconnect and use the property to force the shareability attributes to be programmed into the redistributors and ITSes registers through the GIC quirks mechanism. Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20231006125929.48591-3-lpieralisi@kernel.org
36 lines
1.1 KiB
C
36 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*/
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#ifndef _IRQ_GIC_COMMON_H
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#define _IRQ_GIC_COMMON_H
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#include <linux/of.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/arm-gic-common.h>
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struct gic_quirk {
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const char *desc;
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const char *compatible;
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const char *property;
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bool (*init)(void *data);
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u32 iidr;
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u32 mask;
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};
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int gic_configure_irq(unsigned int irq, unsigned int type,
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void __iomem *base, void (*sync_access)(void));
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void gic_dist_config(void __iomem *base, int gic_irqs,
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void (*sync_access)(void));
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void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void));
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void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
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void *data);
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void gic_enable_of_quirks(const struct device_node *np,
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const struct gic_quirk *quirks, void *data);
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#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
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#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
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#define RDIST_FLAGS_FORCE_NON_SHAREABLE (1 << 2)
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#endif /* _IRQ_GIC_COMMON_H */
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