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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-28 11:49:32 +00:00
![abdoulaye berthe](/assets/img/avatar_default.png)
Signed-off-by: abdoulaye berthe <berthe.ab@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
444 lines
11 KiB
C
444 lines
11 KiB
C
/*
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* Copyright (c) 2011 Jamie Iles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* All enquiries to support@picochip.com
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*/
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#include <linux/basic_mmio_gpio.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define GPIO_SWPORTA_DR 0x00
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#define GPIO_SWPORTA_DDR 0x04
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#define GPIO_SWPORTB_DR 0x0c
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#define GPIO_SWPORTB_DDR 0x10
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#define GPIO_SWPORTC_DR 0x18
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#define GPIO_SWPORTC_DDR 0x1c
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#define GPIO_SWPORTD_DR 0x24
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#define GPIO_SWPORTD_DDR 0x28
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#define GPIO_INTEN 0x30
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#define GPIO_INTMASK 0x34
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INT_POLARITY 0x3c
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#define GPIO_INTSTATUS 0x40
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#define GPIO_PORTA_EOI 0x4c
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#define GPIO_EXT_PORTA 0x50
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#define GPIO_EXT_PORTB 0x54
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#define GPIO_EXT_PORTC 0x58
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#define GPIO_EXT_PORTD 0x5c
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#define DWAPB_MAX_PORTS 4
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#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
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#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
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#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
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struct dwapb_gpio;
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struct dwapb_gpio_port {
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struct bgpio_chip bgc;
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bool is_registered;
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struct dwapb_gpio *gpio;
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};
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struct dwapb_gpio {
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struct device *dev;
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void __iomem *regs;
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struct dwapb_gpio_port *ports;
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unsigned int nr_ports;
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struct irq_domain *domain;
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};
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static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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struct dwapb_gpio_port *port = container_of(bgc, struct
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dwapb_gpio_port, bgc);
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struct dwapb_gpio *gpio = port->gpio;
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return irq_find_mapping(gpio->domain, offset);
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}
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static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
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{
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u32 v = readl(gpio->regs + GPIO_INT_POLARITY);
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if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
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v &= ~BIT(offs);
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else
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v |= BIT(offs);
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writel(v, gpio->regs + GPIO_INT_POLARITY);
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}
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static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
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{
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struct dwapb_gpio *gpio = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
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while (irq_status) {
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int hwirq = fls(irq_status) - 1;
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int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
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generic_handle_irq(gpio_irq);
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irq_status &= ~BIT(hwirq);
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if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
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== IRQ_TYPE_EDGE_BOTH)
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dwapb_toggle_trigger(gpio, hwirq);
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}
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if (chip->irq_eoi)
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chip->irq_eoi(irq_desc_get_irq_data(desc));
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}
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static void dwapb_irq_enable(struct irq_data *d)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct bgpio_chip *bgc = &gpio->ports[0].bgc;
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&bgc->lock, flags);
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val = readl(gpio->regs + GPIO_INTEN);
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val |= BIT(d->hwirq);
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writel(val, gpio->regs + GPIO_INTEN);
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spin_unlock_irqrestore(&bgc->lock, flags);
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}
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static void dwapb_irq_disable(struct irq_data *d)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct bgpio_chip *bgc = &gpio->ports[0].bgc;
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&bgc->lock, flags);
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val = readl(gpio->regs + GPIO_INTEN);
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val &= ~BIT(d->hwirq);
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writel(val, gpio->regs + GPIO_INTEN);
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spin_unlock_irqrestore(&bgc->lock, flags);
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}
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static int dwapb_irq_reqres(struct irq_data *d)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct bgpio_chip *bgc = &gpio->ports[0].bgc;
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if (gpio_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
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dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
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irqd_to_hwirq(d));
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return -EINVAL;
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}
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return 0;
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}
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static void dwapb_irq_relres(struct irq_data *d)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct bgpio_chip *bgc = &gpio->ports[0].bgc;
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gpio_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
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}
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static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct bgpio_chip *bgc = &gpio->ports[0].bgc;
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int bit = d->hwirq;
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unsigned long level, polarity, flags;
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if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
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IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
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return -EINVAL;
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spin_lock_irqsave(&bgc->lock, flags);
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level = readl(gpio->regs + GPIO_INTTYPE_LEVEL);
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polarity = readl(gpio->regs + GPIO_INT_POLARITY);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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level |= BIT(bit);
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dwapb_toggle_trigger(gpio, bit);
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break;
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case IRQ_TYPE_EDGE_RISING:
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level |= BIT(bit);
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polarity |= BIT(bit);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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level |= BIT(bit);
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polarity &= ~BIT(bit);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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level &= ~BIT(bit);
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polarity |= BIT(bit);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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level &= ~BIT(bit);
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polarity &= ~BIT(bit);
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break;
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}
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irq_setup_alt_chip(d, type);
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writel(level, gpio->regs + GPIO_INTTYPE_LEVEL);
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writel(polarity, gpio->regs + GPIO_INT_POLARITY);
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spin_unlock_irqrestore(&bgc->lock, flags);
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return 0;
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}
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static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
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struct dwapb_gpio_port *port)
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{
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struct gpio_chip *gc = &port->bgc.gc;
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struct device_node *node = gc->of_node;
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struct irq_chip_generic *irq_gc;
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unsigned int hwirq, ngpio = gc->ngpio;
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struct irq_chip_type *ct;
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int err, irq, i;
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irq = irq_of_parse_and_map(node, 0);
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if (!irq) {
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dev_warn(gpio->dev, "no irq for bank %s\n",
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port->bgc.gc.of_node->full_name);
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return;
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}
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gpio->domain = irq_domain_add_linear(node, ngpio,
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&irq_generic_chip_ops, gpio);
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if (!gpio->domain)
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return;
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err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
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"gpio-dwapb", handle_level_irq,
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IRQ_NOREQUEST, 0,
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IRQ_GC_INIT_NESTED_LOCK);
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if (err) {
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dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
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irq_domain_remove(gpio->domain);
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gpio->domain = NULL;
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return;
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}
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irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
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if (!irq_gc) {
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irq_domain_remove(gpio->domain);
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gpio->domain = NULL;
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return;
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}
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irq_gc->reg_base = gpio->regs;
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irq_gc->private = gpio;
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for (i = 0; i < 2; i++) {
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ct = &irq_gc->chip_types[i];
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->chip.irq_set_type = dwapb_irq_set_type;
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ct->chip.irq_enable = dwapb_irq_enable;
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ct->chip.irq_disable = dwapb_irq_disable;
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ct->chip.irq_request_resources = dwapb_irq_reqres;
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ct->chip.irq_release_resources = dwapb_irq_relres;
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ct->regs.ack = GPIO_PORTA_EOI;
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ct->regs.mask = GPIO_INTMASK;
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ct->type = IRQ_TYPE_LEVEL_MASK;
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}
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irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
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irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
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irq_gc->chip_types[1].handler = handle_edge_irq;
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irq_set_chained_handler(irq, dwapb_irq_handler);
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irq_set_handler_data(irq, gpio);
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for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
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irq_create_mapping(gpio->domain, hwirq);
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port->bgc.gc.to_irq = dwapb_gpio_to_irq;
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}
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static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
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{
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struct dwapb_gpio_port *port = &gpio->ports[0];
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struct gpio_chip *gc = &port->bgc.gc;
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unsigned int ngpio = gc->ngpio;
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irq_hw_number_t hwirq;
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if (!gpio->domain)
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return;
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for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
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irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
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irq_domain_remove(gpio->domain);
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gpio->domain = NULL;
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}
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static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
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struct device_node *port_np,
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unsigned int offs)
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{
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struct dwapb_gpio_port *port;
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u32 port_idx, ngpio;
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void __iomem *dat, *set, *dirout;
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int err;
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if (of_property_read_u32(port_np, "reg", &port_idx) ||
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port_idx >= DWAPB_MAX_PORTS) {
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dev_err(gpio->dev, "missing/invalid port index for %s\n",
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port_np->full_name);
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return -EINVAL;
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}
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port = &gpio->ports[offs];
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port->gpio = gpio;
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if (of_property_read_u32(port_np, "snps,nr-gpios", &ngpio)) {
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dev_info(gpio->dev, "failed to get number of gpios for %s\n",
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port_np->full_name);
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ngpio = 32;
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}
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dat = gpio->regs + GPIO_EXT_PORTA + (port_idx * GPIO_EXT_PORT_SIZE);
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set = gpio->regs + GPIO_SWPORTA_DR + (port_idx * GPIO_SWPORT_DR_SIZE);
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dirout = gpio->regs + GPIO_SWPORTA_DDR +
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(port_idx * GPIO_SWPORT_DDR_SIZE);
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err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
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NULL, false);
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if (err) {
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dev_err(gpio->dev, "failed to init gpio chip for %s\n",
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port_np->full_name);
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return err;
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}
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port->bgc.gc.ngpio = ngpio;
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port->bgc.gc.of_node = port_np;
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/*
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* Only port A can provide interrupts in all configurations of the IP.
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*/
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if (port_idx == 0 &&
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of_property_read_bool(port_np, "interrupt-controller"))
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dwapb_configure_irqs(gpio, port);
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err = gpiochip_add(&port->bgc.gc);
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if (err)
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dev_err(gpio->dev, "failed to register gpiochip for %s\n",
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port_np->full_name);
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else
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port->is_registered = true;
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return err;
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}
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static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
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{
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unsigned int m;
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for (m = 0; m < gpio->nr_ports; ++m)
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if (gpio->ports[m].is_registered)
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gpiochip_remove(&gpio->ports[m].bgc.gc);
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}
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static int dwapb_gpio_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct dwapb_gpio *gpio;
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struct device_node *np;
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int err;
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unsigned int offs = 0;
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gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio)
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return -ENOMEM;
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gpio->dev = &pdev->dev;
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gpio->nr_ports = of_get_child_count(pdev->dev.of_node);
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if (!gpio->nr_ports) {
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err = -EINVAL;
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goto out_err;
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}
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gpio->ports = devm_kzalloc(&pdev->dev, gpio->nr_ports *
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sizeof(*gpio->ports), GFP_KERNEL);
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if (!gpio->ports) {
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err = -ENOMEM;
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goto out_err;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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gpio->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(gpio->regs)) {
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err = PTR_ERR(gpio->regs);
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goto out_err;
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}
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for_each_child_of_node(pdev->dev.of_node, np) {
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err = dwapb_gpio_add_port(gpio, np, offs++);
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if (err)
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goto out_unregister;
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}
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platform_set_drvdata(pdev, gpio);
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return 0;
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out_unregister:
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dwapb_gpio_unregister(gpio);
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dwapb_irq_teardown(gpio);
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out_err:
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return err;
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}
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static int dwapb_gpio_remove(struct platform_device *pdev)
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{
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struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
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dwapb_gpio_unregister(gpio);
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dwapb_irq_teardown(gpio);
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return 0;
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}
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static const struct of_device_id dwapb_of_match[] = {
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{ .compatible = "snps,dw-apb-gpio" },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, dwapb_of_match);
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static struct platform_driver dwapb_gpio_driver = {
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.driver = {
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.name = "gpio-dwapb",
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(dwapb_of_match),
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},
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.probe = dwapb_gpio_probe,
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.remove = dwapb_gpio_remove,
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};
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module_platform_driver(dwapb_gpio_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Jamie Iles");
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MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
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