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![Boris BREZILLON](/assets/img/avatar_default.png)
Define SoCs that need irq fixups before enabling the AIC irqchip. At the moment we're only fixing irq generated by the RTC block, but other fixups will be added later on. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Link: https://lkml.kernel.org/r/1405016741-2407-4-git-send-email-boris.brezillon@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
353 lines
9 KiB
C
353 lines
9 KiB
C
/*
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* Atmel AT91 AIC5 (Advanced Interrupt Controller) driver
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*
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* Copyright (C) 2004 SAN People
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* Copyright (C) 2004 ATMEL
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* Copyright (C) Rick Bronson
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* Copyright (C) 2014 Free Electrons
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/bitmap.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include "irq-atmel-aic-common.h"
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#include "irqchip.h"
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/* Number of irq lines managed by AIC */
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#define NR_AIC5_IRQS 128
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#define AT91_AIC5_SSR 0x0
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#define AT91_AIC5_INTSEL_MSK (0x7f << 0)
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#define AT91_AIC5_SMR 0x4
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#define AT91_AIC5_SVR 0x8
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#define AT91_AIC5_IVR 0x10
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#define AT91_AIC5_FVR 0x14
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#define AT91_AIC5_ISR 0x18
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#define AT91_AIC5_IPR0 0x20
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#define AT91_AIC5_IPR1 0x24
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#define AT91_AIC5_IPR2 0x28
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#define AT91_AIC5_IPR3 0x2c
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#define AT91_AIC5_IMR 0x30
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#define AT91_AIC5_CISR 0x34
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#define AT91_AIC5_IECR 0x40
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#define AT91_AIC5_IDCR 0x44
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#define AT91_AIC5_ICCR 0x48
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#define AT91_AIC5_ISCR 0x4c
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#define AT91_AIC5_EOICR 0x38
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#define AT91_AIC5_SPU 0x3c
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#define AT91_AIC5_DCR 0x6c
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#define AT91_AIC5_FFER 0x50
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#define AT91_AIC5_FFDR 0x54
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#define AT91_AIC5_FFSR 0x58
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static struct irq_domain *aic5_domain;
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static asmlinkage void __exception_irq_entry
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aic5_handle(struct pt_regs *regs)
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{
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struct irq_domain_chip_generic *dgc = aic5_domain->gc;
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struct irq_chip_generic *gc = dgc->gc[0];
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u32 irqnr;
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u32 irqstat;
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irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR);
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irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR);
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irqnr = irq_find_mapping(aic5_domain, irqnr);
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if (!irqstat)
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irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
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else
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handle_IRQ(irqnr, regs);
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}
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static void aic5_mask(struct irq_data *d)
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{
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struct irq_domain *domain = d->domain;
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struct irq_domain_chip_generic *dgc = domain->gc;
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struct irq_chip_generic *gc = dgc->gc[0];
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/* Disable interrupt on AIC5 */
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irq_gc_lock(gc);
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irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
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irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
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gc->mask_cache &= ~d->mask;
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irq_gc_unlock(gc);
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}
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static void aic5_unmask(struct irq_data *d)
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{
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struct irq_domain *domain = d->domain;
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struct irq_domain_chip_generic *dgc = domain->gc;
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struct irq_chip_generic *gc = dgc->gc[0];
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/* Enable interrupt on AIC5 */
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irq_gc_lock(gc);
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irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
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irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR);
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gc->mask_cache |= d->mask;
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irq_gc_unlock(gc);
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}
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static int aic5_retrigger(struct irq_data *d)
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{
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struct irq_domain *domain = d->domain;
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struct irq_domain_chip_generic *dgc = domain->gc;
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struct irq_chip_generic *gc = dgc->gc[0];
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/* Enable interrupt on AIC5 */
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irq_gc_lock(gc);
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irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
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irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR);
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irq_gc_unlock(gc);
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return 0;
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}
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static int aic5_set_type(struct irq_data *d, unsigned type)
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{
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struct irq_domain *domain = d->domain;
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struct irq_domain_chip_generic *dgc = domain->gc;
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struct irq_chip_generic *gc = dgc->gc[0];
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unsigned int smr;
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int ret;
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irq_gc_lock(gc);
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irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
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smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
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ret = aic_common_set_type(d, type, &smr);
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if (!ret)
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irq_reg_writel(smr, gc->reg_base + AT91_AIC5_SMR);
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irq_gc_unlock(gc);
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return ret;
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}
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#ifdef CONFIG_PM
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static void aic5_suspend(struct irq_data *d)
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{
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struct irq_domain *domain = d->domain;
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struct irq_domain_chip_generic *dgc = domain->gc;
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struct irq_chip_generic *bgc = dgc->gc[0];
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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int i;
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u32 mask;
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irq_gc_lock(bgc);
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for (i = 0; i < dgc->irqs_per_chip; i++) {
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mask = 1 << i;
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if ((mask & gc->mask_cache) == (mask & gc->wake_active))
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continue;
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irq_reg_writel(i + gc->irq_base,
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bgc->reg_base + AT91_AIC5_SSR);
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if (mask & gc->wake_active)
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irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
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else
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irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
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}
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irq_gc_unlock(bgc);
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}
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static void aic5_resume(struct irq_data *d)
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{
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struct irq_domain *domain = d->domain;
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struct irq_domain_chip_generic *dgc = domain->gc;
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struct irq_chip_generic *bgc = dgc->gc[0];
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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int i;
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u32 mask;
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irq_gc_lock(bgc);
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for (i = 0; i < dgc->irqs_per_chip; i++) {
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mask = 1 << i;
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if ((mask & gc->mask_cache) == (mask & gc->wake_active))
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continue;
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irq_reg_writel(i + gc->irq_base,
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bgc->reg_base + AT91_AIC5_SSR);
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if (mask & gc->mask_cache)
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irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
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else
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irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
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}
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irq_gc_unlock(bgc);
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}
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static void aic5_pm_shutdown(struct irq_data *d)
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{
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struct irq_domain *domain = d->domain;
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struct irq_domain_chip_generic *dgc = domain->gc;
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struct irq_chip_generic *bgc = dgc->gc[0];
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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int i;
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irq_gc_lock(bgc);
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for (i = 0; i < dgc->irqs_per_chip; i++) {
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irq_reg_writel(i + gc->irq_base,
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bgc->reg_base + AT91_AIC5_SSR);
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irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
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irq_reg_writel(1, bgc->reg_base + AT91_AIC5_ICCR);
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}
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irq_gc_unlock(bgc);
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}
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#else
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#define aic5_suspend NULL
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#define aic5_resume NULL
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#define aic5_pm_shutdown NULL
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#endif /* CONFIG_PM */
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static void __init aic5_hw_init(struct irq_domain *domain)
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{
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
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int i;
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/*
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* Perform 8 End Of Interrupt Command to make sure AIC
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* will not Lock out nIRQ
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*/
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for (i = 0; i < 8; i++)
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irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
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/*
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* Spurious Interrupt ID in Spurious Vector Register.
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* When there is no current interrupt, the IRQ Vector Register
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* reads the value stored in AIC_SPU
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*/
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irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC5_SPU);
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/* No debugging in AIC: Debug (Protect) Control Register */
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irq_reg_writel(0, gc->reg_base + AT91_AIC5_DCR);
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/* Disable and clear all interrupts initially */
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for (i = 0; i < domain->revmap_size; i++) {
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irq_reg_writel(i, gc->reg_base + AT91_AIC5_SSR);
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irq_reg_writel(i, gc->reg_base + AT91_AIC5_SVR);
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irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
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irq_reg_writel(1, gc->reg_base + AT91_AIC5_ICCR);
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}
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}
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static int aic5_irq_domain_xlate(struct irq_domain *d,
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struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_type)
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{
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struct irq_domain_chip_generic *dgc = d->gc;
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struct irq_chip_generic *gc;
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unsigned smr;
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int ret;
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if (!dgc)
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return -EINVAL;
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ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
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out_hwirq, out_type);
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if (ret)
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return ret;
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gc = dgc->gc[0];
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irq_gc_lock(gc);
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irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR);
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smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
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ret = aic_common_set_priority(intspec[2], &smr);
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if (!ret)
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irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR);
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irq_gc_unlock(gc);
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return ret;
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}
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static const struct irq_domain_ops aic5_irq_ops = {
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.map = irq_map_generic_chip,
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.xlate = aic5_irq_domain_xlate,
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};
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static void __init sama5d3_aic_irq_fixup(struct device_node *root)
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{
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aic_common_rtc_irq_fixup(root);
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}
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static const struct of_device_id __initdata aic5_irq_fixups[] = {
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{ .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
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{ /* sentinel */ },
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};
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static int __init aic5_of_init(struct device_node *node,
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struct device_node *parent,
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int nirqs)
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{
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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int nchips;
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int i;
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if (nirqs > NR_AIC5_IRQS)
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return -EINVAL;
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if (aic5_domain)
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return -EEXIST;
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domain = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5",
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nirqs);
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if (IS_ERR(domain))
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return PTR_ERR(domain);
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aic_common_irq_fixup(aic5_irq_fixups);
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aic5_domain = domain;
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nchips = aic5_domain->revmap_size / 32;
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for (i = 0; i < nchips; i++) {
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gc = irq_get_domain_generic_chip(domain, i * 32);
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gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;
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gc->chip_types[0].chip.irq_mask = aic5_mask;
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gc->chip_types[0].chip.irq_unmask = aic5_unmask;
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gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;
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gc->chip_types[0].chip.irq_set_type = aic5_set_type;
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gc->chip_types[0].chip.irq_suspend = aic5_suspend;
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gc->chip_types[0].chip.irq_resume = aic5_resume;
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gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;
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}
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aic5_hw_init(domain);
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set_handle_irq(aic5_handle);
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return 0;
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}
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#define NR_SAMA5D3_IRQS 50
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static int __init sama5d3_aic5_of_init(struct device_node *node,
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struct device_node *parent)
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{
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return aic5_of_init(node, parent, NR_SAMA5D3_IRQS);
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}
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IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init);
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