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![Nishanth Menon](/assets/img/avatar_default.png)
On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10, 131, 132, 133 are direct wired to hardware blocks bypassing crossbar. This quirky implementation is *NOT* supposed to be the expectation of crossbar hardware usage. However, these are already marked in our description of the hardware with SKIP and RESERVED where appropriate. Unfortunately, we need to be able to refer to these hardwired IRQs. So, to request these, crossbar driver can use the existing information from it's table that these SKIP/RESERVED maps are direct wired sources and generic allocation/programming of crossbar should be avoided. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Link: https://lkml.kernel.org/r/1403766634-18543-17-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
326 lines
7.2 KiB
C
326 lines
7.2 KiB
C
/*
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* drivers/irqchip/irq-crossbar.c
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
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* Author: Sricharan R <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/irq-crossbar.h>
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#define IRQ_FREE -1
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#define IRQ_RESERVED -2
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#define IRQ_SKIP -3
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#define GIC_IRQ_START 32
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/**
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* struct crossbar_device - crossbar device description
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* @int_max: maximum number of supported interrupts
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* @safe_map: safe default value to initialize the crossbar
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* @max_crossbar_sources: Maximum number of crossbar sources
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* @irq_map: array of interrupts to crossbar number mapping
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* @crossbar_base: crossbar base address
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* @register_offsets: offsets for each irq number
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* @write: register write function pointer
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*/
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struct crossbar_device {
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uint int_max;
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uint safe_map;
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uint max_crossbar_sources;
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uint *irq_map;
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void __iomem *crossbar_base;
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int *register_offsets;
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void (*write)(int, int);
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};
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static struct crossbar_device *cb;
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static inline void crossbar_writel(int irq_no, int cb_no)
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{
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writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline void crossbar_writew(int irq_no, int cb_no)
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{
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writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline void crossbar_writeb(int irq_no, int cb_no)
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{
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writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline int get_prev_map_irq(int cb_no)
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{
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int i;
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for (i = cb->int_max - 1; i >= 0; i--)
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if (cb->irq_map[i] == cb_no)
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return i;
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return -ENODEV;
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}
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static inline int allocate_free_irq(int cb_no)
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{
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int i;
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for (i = cb->int_max - 1; i >= 0; i--) {
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if (cb->irq_map[i] == IRQ_FREE) {
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cb->irq_map[i] = cb_no;
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return i;
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}
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}
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return -ENODEV;
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}
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static inline bool needs_crossbar_write(irq_hw_number_t hw)
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{
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int cb_no;
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if (hw > GIC_IRQ_START) {
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cb_no = cb->irq_map[hw - GIC_IRQ_START];
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if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP)
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return true;
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}
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return false;
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}
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static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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if (needs_crossbar_write(hw))
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cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
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return 0;
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}
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/**
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* crossbar_domain_unmap - unmap a crossbar<->irq connection
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* @d: domain of irq to unmap
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* @irq: virq number
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*
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* We do not maintain a use count of total number of map/unmap
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* calls for a particular irq to find out if a irq can be really
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* unmapped. This is because unmap is called during irq_dispose_mapping(irq),
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* after which irq is anyways unusable. So an explicit map has to be called
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* after that.
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*/
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static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
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if (needs_crossbar_write(hw)) {
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cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
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cb->write(hw - GIC_IRQ_START, cb->safe_map);
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}
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}
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static int crossbar_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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int ret;
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int req_num = intspec[1];
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int direct_map_num;
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if (req_num >= cb->max_crossbar_sources) {
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direct_map_num = req_num - cb->max_crossbar_sources;
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if (direct_map_num < cb->int_max) {
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ret = cb->irq_map[direct_map_num];
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if (ret == IRQ_RESERVED || ret == IRQ_SKIP) {
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/* We use the interrupt num as h/w irq num */
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ret = direct_map_num;
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goto found;
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}
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}
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pr_err("%s: requested crossbar number %d > max %d\n",
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__func__, req_num, cb->max_crossbar_sources);
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return -EINVAL;
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}
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ret = get_prev_map_irq(req_num);
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if (ret >= 0)
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goto found;
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ret = allocate_free_irq(req_num);
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if (ret < 0)
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return ret;
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found:
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*out_hwirq = ret + GIC_IRQ_START;
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return 0;
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}
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static const struct irq_domain_ops routable_irq_domain_ops = {
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.map = crossbar_domain_map,
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.unmap = crossbar_domain_unmap,
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.xlate = crossbar_domain_xlate
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};
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static int __init crossbar_of_init(struct device_node *node)
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{
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int i, size, max = 0, reserved = 0, entry;
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const __be32 *irqsr;
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int ret = -ENOMEM;
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cb = kzalloc(sizeof(*cb), GFP_KERNEL);
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if (!cb)
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return ret;
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cb->crossbar_base = of_iomap(node, 0);
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if (!cb->crossbar_base)
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goto err_cb;
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of_property_read_u32(node, "ti,max-crossbar-sources",
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&cb->max_crossbar_sources);
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if (!cb->max_crossbar_sources) {
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pr_err("missing 'ti,max-crossbar-sources' property\n");
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ret = -EINVAL;
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goto err_base;
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}
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of_property_read_u32(node, "ti,max-irqs", &max);
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if (!max) {
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pr_err("missing 'ti,max-irqs' property\n");
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ret = -EINVAL;
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goto err_base;
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}
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cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
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if (!cb->irq_map)
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goto err_base;
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cb->int_max = max;
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for (i = 0; i < max; i++)
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cb->irq_map[i] = IRQ_FREE;
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/* Get and mark reserved irqs */
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irqsr = of_get_property(node, "ti,irqs-reserved", &size);
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if (irqsr) {
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size /= sizeof(__be32);
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for (i = 0; i < size; i++) {
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of_property_read_u32_index(node,
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"ti,irqs-reserved",
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i, &entry);
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if (entry > max) {
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pr_err("Invalid reserved entry\n");
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ret = -EINVAL;
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goto err_irq_map;
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}
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cb->irq_map[entry] = IRQ_RESERVED;
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}
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}
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/* Skip irqs hardwired to bypass the crossbar */
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irqsr = of_get_property(node, "ti,irqs-skip", &size);
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if (irqsr) {
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size /= sizeof(__be32);
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for (i = 0; i < size; i++) {
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of_property_read_u32_index(node,
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"ti,irqs-skip",
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i, &entry);
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if (entry > max) {
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pr_err("Invalid skip entry\n");
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ret = -EINVAL;
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goto err_irq_map;
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}
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cb->irq_map[entry] = IRQ_SKIP;
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}
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}
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cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
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if (!cb->register_offsets)
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goto err_irq_map;
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of_property_read_u32(node, "ti,reg-size", &size);
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switch (size) {
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case 1:
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cb->write = crossbar_writeb;
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break;
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case 2:
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cb->write = crossbar_writew;
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break;
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case 4:
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cb->write = crossbar_writel;
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break;
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default:
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pr_err("Invalid reg-size property\n");
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ret = -EINVAL;
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goto err_reg_offset;
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break;
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}
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/*
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* Register offsets are not linear because of the
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* reserved irqs. so find and store the offsets once.
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*/
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for (i = 0; i < max; i++) {
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if (cb->irq_map[i] == IRQ_RESERVED)
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continue;
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cb->register_offsets[i] = reserved;
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reserved += size;
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}
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of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
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/* Initialize the crossbar with safe map to start with */
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for (i = 0; i < max; i++) {
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if (cb->irq_map[i] == IRQ_RESERVED ||
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cb->irq_map[i] == IRQ_SKIP)
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continue;
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cb->write(i, cb->safe_map);
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}
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register_routable_domain_ops(&routable_irq_domain_ops);
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return 0;
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err_reg_offset:
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kfree(cb->register_offsets);
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err_irq_map:
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kfree(cb->irq_map);
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err_base:
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iounmap(cb->crossbar_base);
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err_cb:
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kfree(cb);
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cb = NULL;
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return ret;
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}
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static const struct of_device_id crossbar_match[] __initconst = {
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{ .compatible = "ti,irq-crossbar" },
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{}
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};
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int __init irqcrossbar_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, crossbar_match);
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if (!np)
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return -ENODEV;
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crossbar_of_init(np);
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return 0;
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}
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