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85e4db5347
The display control registers for primary and secondary display share some of the bits and those bits can be defined in a single place and then used for manipulations of the relevant registers. Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
233 lines
7 KiB
C
233 lines
7 KiB
C
#include "ddk750_reg.h"
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#include "ddk750_help.h"
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#include "ddk750_display.h"
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#include "ddk750_power.h"
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#include "ddk750_dvi.h"
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#define primaryWaitVerticalSync(delay) waitNextVerticalSync(0, delay)
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static void setDisplayControl(int ctrl, int disp_state)
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{
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/* state != 0 means turn on both timing & plane en_bit */
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unsigned long reg, reserved;
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int cnt;
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cnt = 0;
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/* Set the primary display control */
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if (!ctrl) {
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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/* Turn on/off the Panel display control */
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if (disp_state) {
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/* Timing should be enabled first before enabling the plane
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* because changing at the same time does not guarantee that
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* the plane will also enabled or disabled.
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*/
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reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, ENABLE);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, ENABLE);
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/* Added some masks to mask out the reserved bits.
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* Sometimes, the reserved bits are set/reset randomly when
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* writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
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* reserved bits are needed to be masked out.
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*/
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reserved = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
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FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
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FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE);
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/* Somehow the register value on the plane is not set
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* until a few delay. Need to write
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* and read it a couple times
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*/
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do {
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cnt++;
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POKE32(PANEL_DISPLAY_CTRL, reg);
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} while ((PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) !=
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(reg & ~reserved));
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printk("Set Panel Plane enbit:after tried %d times\n", cnt);
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} else {
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/* When turning off, there is no rule on the programming
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* sequence since whenever the clock is off, then it does not
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* matter whether the plane is enabled or disabled.
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* Note: Modifying the plane bit will take effect on the
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* next vertical sync. Need to find out if it is necessary to
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* wait for 1 vsync before modifying the timing enable bit.
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* */
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reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, DISABLE);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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}
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} else {
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/* Set the secondary display control */
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reg = PEEK32(CRT_DISPLAY_CTRL);
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if (disp_state) {
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/* Timing should be enabled first before enabling the plane because changing at the
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same time does not guarantee that the plane will also enabled or disabled.
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*/
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reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, ENABLE);
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POKE32(CRT_DISPLAY_CTRL, reg);
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reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, ENABLE);
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/* Added some masks to mask out the reserved bits.
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* Sometimes, the reserved bits are set/reset randomly when
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* writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
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* reserved bits are needed to be masked out.
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*/
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reserved = FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
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FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
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FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) |
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FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_4_MASK, ENABLE);
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do {
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cnt++;
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POKE32(CRT_DISPLAY_CTRL, reg);
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} while ((PEEK32(CRT_DISPLAY_CTRL) & ~reserved) !=
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(reg & ~reserved));
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printk("Set Crt Plane enbit:after tried %d times\n", cnt);
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} else {
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/* When turning off, there is no rule on the programming
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* sequence since whenever the clock is off, then it does not
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* matter whether the plane is enabled or disabled.
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* Note: Modifying the plane bit will take effect on the next
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* vertical sync. Need to find out if it is necessary to
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* wait for 1 vsync before modifying the timing enable bit.
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*/
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reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
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POKE32(CRT_DISPLAY_CTRL, reg);
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reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, DISABLE);
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POKE32(CRT_DISPLAY_CTRL, reg);
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}
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}
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}
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static void waitNextVerticalSync(int ctrl, int delay)
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{
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unsigned int status;
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if (!ctrl) {
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/* primary controller */
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/* Do not wait when the Primary PLL is off or display control is already off.
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This will prevent the software to wait forever. */
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if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
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(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL),
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DISPLAY_CTRL, TIMING) ==
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DISPLAY_CTRL_TIMING_DISABLE)) {
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return;
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}
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while (delay-- > 0) {
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/* Wait for end of vsync. */
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do {
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status = PEEK32(SYSTEM_CTRL);
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} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
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/* Wait for start of vsync. */
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do {
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status = PEEK32(SYSTEM_CTRL);
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} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
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}
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} else {
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/* Do not wait when the Primary PLL is off or display control is already off.
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This will prevent the software to wait forever. */
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if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) ||
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(FIELD_GET(PEEK32(CRT_DISPLAY_CTRL),
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DISPLAY_CTRL, TIMING) ==
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DISPLAY_CTRL_TIMING_DISABLE)) {
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return;
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}
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while (delay-- > 0) {
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/* Wait for end of vsync. */
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do {
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status = PEEK32(SYSTEM_CTRL);
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} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
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/* Wait for start of vsync. */
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do {
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status = PEEK32(SYSTEM_CTRL);
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} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
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}
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}
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}
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static void swPanelPowerSequence(int disp, int delay)
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{
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unsigned int reg;
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/* disp should be 1 to open sequence */
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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primaryWaitVerticalSync(delay);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, DATA, disp);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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primaryWaitVerticalSync(delay);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, VBIASEN, disp);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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primaryWaitVerticalSync(delay);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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primaryWaitVerticalSync(delay);
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}
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void ddk750_setLogicalDispOut(disp_output_t output)
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{
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unsigned int reg;
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if (output & PNL_2_USAGE) {
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/* set panel path controller select */
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, SELECT, (output & PNL_2_MASK)>>PNL_2_OFFSET);
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POKE32(PANEL_DISPLAY_CTRL, reg);
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}
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if (output & CRT_2_USAGE) {
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/* set crt path controller select */
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reg = PEEK32(CRT_DISPLAY_CTRL);
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reg = FIELD_VALUE(reg, CRT_DISPLAY_CTRL, SELECT, (output & CRT_2_MASK)>>CRT_2_OFFSET);
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/*se blank off */
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reg = FIELD_SET(reg, CRT_DISPLAY_CTRL, BLANK, OFF);
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POKE32(CRT_DISPLAY_CTRL, reg);
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}
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if (output & PRI_TP_USAGE) {
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/* set primary timing and plane en_bit */
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setDisplayControl(0, (output & PRI_TP_MASK) >> PRI_TP_OFFSET);
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}
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if (output & SEC_TP_USAGE) {
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/* set secondary timing and plane en_bit*/
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setDisplayControl(1, (output & SEC_TP_MASK) >> SEC_TP_OFFSET);
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}
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if (output & PNL_SEQ_USAGE) {
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/* set panel sequence */
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swPanelPowerSequence((output & PNL_SEQ_MASK) >> PNL_SEQ_OFFSET, 4);
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}
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if (output & DAC_USAGE)
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setDAC((output & DAC_MASK) >> DAC_OFFSET);
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if (output & DPMS_USAGE)
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ddk750_setDPMS((output & DPMS_MASK) >> DPMS_OFFSET);
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}
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