Paul Cercueil 868b70b9e6 MIPS: DTS: CI20: Parent MSCMUX clock to MPLL ... This makes it possible to clock the SD cards much higher, as the MPLL is running at 1.2 GHz by default. The previous parent was the EXT clock, which caused the SD cards to be clocked at 24 MHz maximum. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>		2023-06-09 09:55:38 +02:00
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compressed	mips: boot/compressed: use __NO_FORTIFY	2022-11-11 15:43:26 +01:00
dts	MIPS: DTS: CI20: Parent MSCMUX clock to MPLL	2023-06-09 09:55:38 +02:00
tools	ELF: fix all "Elf" typos	2023-04-08 13:45:37 -07:00
.gitignore	mips: boot: clean up self-extracting targets scenarios	2020-11-12 23:46:45 +01:00
ecoff.h	MIPS: Make elf2ecoff work on 64bit host machines	2018-06-24 09:25:24 -07:00
elf2ecoff.c	MIPS: Make elf2ecoff work on 64bit host machines	2018-06-24 09:25:24 -07:00
Makefile	kbuild: use more subdir- for visiting subdirectories while cleaning	2021-10-24 13:49:46 +09:00