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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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56ba355d6b
MT8173 HDMI hardware has a output control bit to enable/disable HDMI output. Because of security reason, so this bit can ONLY be controlled in ARM supervisor mode. Now the only way to enter ARM supervisor is the ARM trusted firmware. So atf provides a API for HDMI driver to call to setup this HDMI control bit to enable HDMI output in supervisor mode. Signed-off-by: Jie Qiu <jie.qiu@mediatek.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
238 lines
7.1 KiB
C
238 lines
7.1 KiB
C
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MTK_HDMI_REGS_H
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#define _MTK_HDMI_REGS_H
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#define GRL_INT_MASK 0x18
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#define GRL_IFM_PORT 0x188
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#define GRL_CH_SWAP 0x198
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#define LR_SWAP BIT(0)
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#define LFE_CC_SWAP BIT(1)
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#define LSRS_SWAP BIT(2)
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#define RLS_RRS_SWAP BIT(3)
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#define LR_STATUS_SWAP BIT(4)
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#define GRL_I2S_C_STA0 0x140
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#define GRL_I2S_C_STA1 0x144
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#define GRL_I2S_C_STA2 0x148
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#define GRL_I2S_C_STA3 0x14C
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#define GRL_I2S_C_STA4 0x150
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#define GRL_I2S_UV 0x154
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#define I2S_UV_V BIT(0)
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#define I2S_UV_U BIT(1)
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#define I2S_UV_CH_EN_MASK 0x3c
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#define I2S_UV_CH_EN(x) BIT((x) + 2)
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#define I2S_UV_TMDS_DEBUG BIT(6)
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#define I2S_UV_NORMAL_INFO_INV BIT(7)
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#define GRL_ACP_ISRC_CTRL 0x158
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#define VS_EN BIT(0)
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#define ACP_EN BIT(1)
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#define ISRC1_EN BIT(2)
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#define ISRC2_EN BIT(3)
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#define GAMUT_EN BIT(4)
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#define GRL_CTS_CTRL 0x160
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#define CTS_CTRL_SOFT BIT(0)
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#define GRL_INT 0x14
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#define INT_MDI BIT(0)
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#define INT_HDCP BIT(1)
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#define INT_FIFO_O BIT(2)
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#define INT_FIFO_U BIT(3)
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#define INT_IFM_ERR BIT(4)
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#define INT_INF_DONE BIT(5)
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#define INT_NCTS_DONE BIT(6)
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#define INT_CTRL_PKT_DONE BIT(7)
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#define GRL_INT_MASK 0x18
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#define GRL_CTRL 0x1C
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#define CTRL_GEN_EN BIT(2)
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#define CTRL_SPD_EN BIT(3)
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#define CTRL_MPEG_EN BIT(4)
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#define CTRL_AUDIO_EN BIT(5)
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#define CTRL_AVI_EN BIT(6)
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#define CTRL_AVMUTE BIT(7)
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#define GRL_STATUS 0x20
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#define STATUS_HTPLG BIT(0)
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#define STATUS_PORD BIT(1)
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#define GRL_DIVN 0x170
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#define NCTS_WRI_ANYTIME BIT(6)
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#define GRL_AUDIO_CFG 0x17C
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#define AUDIO_ZERO BIT(0)
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#define HIGH_BIT_RATE BIT(1)
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#define SACD_DST BIT(2)
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#define DST_NORMAL_DOUBLE BIT(3)
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#define DSD_INV BIT(4)
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#define LR_INV BIT(5)
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#define LR_MIX BIT(6)
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#define DSD_SEL BIT(7)
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#define GRL_NCTS 0x184
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#define GRL_CH_SW0 0x18C
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#define GRL_CH_SW1 0x190
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#define GRL_CH_SW2 0x194
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#define CH_SWITCH(from, to) ((from) << ((to) * 3))
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#define GRL_INFOFRM_VER 0x19C
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#define GRL_INFOFRM_TYPE 0x1A0
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#define GRL_INFOFRM_LNG 0x1A4
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#define GRL_MIX_CTRL 0x1B4
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#define MIX_CTRL_SRC_EN BIT(0)
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#define BYPASS_VOLUME BIT(1)
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#define MIX_CTRL_FLAT BIT(7)
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#define GRL_AOUT_CFG 0x1C4
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#define AOUT_BNUM_SEL_MASK 0x03
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#define AOUT_24BIT 0x00
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#define AOUT_20BIT 0x02
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#define AOUT_16BIT 0x03
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#define AOUT_FIFO_ADAP_CTRL BIT(6)
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#define AOUT_BURST_PREAMBLE_EN BIT(7)
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#define HIGH_BIT_RATE_PACKET_ALIGN (AOUT_BURST_PREAMBLE_EN | \
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AOUT_FIFO_ADAP_CTRL)
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#define GRL_SHIFT_L1 0x1C0
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#define GRL_SHIFT_R2 0x1B0
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#define AUDIO_PACKET_OFF BIT(6)
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#define GRL_CFG0 0x24
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#define CFG0_I2S_MODE_MASK 0x3
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#define CFG0_I2S_MODE_RTJ 0x1
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#define CFG0_I2S_MODE_LTJ 0x0
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#define CFG0_I2S_MODE_I2S 0x2
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#define CFG0_W_LENGTH_MASK 0x30
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#define CFG0_W_LENGTH_24BIT 0x00
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#define CFG0_W_LENGTH_16BIT 0x10
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#define GRL_CFG1 0x28
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#define CFG1_EDG_SEL BIT(0)
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#define CFG1_SPDIF BIT(1)
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#define CFG1_DVI BIT(2)
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#define CFG1_HDCP_DEBUG BIT(3)
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#define GRL_CFG2 0x2c
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#define CFG2_MHL_DE_SEL BIT(3)
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#define CFG2_MHL_FAKE_DE_SEL BIT(4)
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#define CFG2_MHL_DATA_REMAP BIT(5)
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#define CFG2_NOTICE_EN BIT(6)
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#define CFG2_ACLK_INV BIT(7)
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#define GRL_CFG3 0x30
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#define CFG3_AES_KEY_INDEX_MASK 0x3f
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#define CFG3_CONTROL_PACKET_DELAY BIT(6)
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#define CFG3_KSV_LOAD_START BIT(7)
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#define GRL_CFG4 0x34
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#define CFG4_AES_KEY_LOAD BIT(4)
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#define CFG4_AV_UNMUTE_EN BIT(5)
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#define CFG4_AV_UNMUTE_SET BIT(6)
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#define CFG4_MHL_MODE BIT(7)
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#define GRL_CFG5 0x38
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#define CFG5_CD_RATIO_MASK 0x8F
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#define CFG5_FS128 (0x1 << 4)
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#define CFG5_FS256 (0x2 << 4)
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#define CFG5_FS384 (0x3 << 4)
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#define CFG5_FS512 (0x4 << 4)
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#define CFG5_FS768 (0x6 << 4)
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#define DUMMY_304 0x304
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#define CHMO_SEL (0x3 << 2)
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#define CHM1_SEL (0x3 << 4)
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#define CHM2_SEL (0x3 << 6)
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#define AUDIO_I2S_NCTS_SEL BIT(1)
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#define AUDIO_I2S_NCTS_SEL_64 (1 << 1)
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#define AUDIO_I2S_NCTS_SEL_128 (0 << 1)
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#define NEW_GCP_CTRL BIT(0)
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#define NEW_GCP_CTRL_MERGE BIT(0)
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#define GRL_L_STATUS_0 0x200
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#define GRL_L_STATUS_1 0x204
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#define GRL_L_STATUS_2 0x208
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#define GRL_L_STATUS_3 0x20c
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#define GRL_L_STATUS_4 0x210
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#define GRL_L_STATUS_5 0x214
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#define GRL_L_STATUS_6 0x218
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#define GRL_L_STATUS_7 0x21c
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#define GRL_L_STATUS_8 0x220
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#define GRL_L_STATUS_9 0x224
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#define GRL_L_STATUS_10 0x228
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#define GRL_L_STATUS_11 0x22c
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#define GRL_L_STATUS_12 0x230
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#define GRL_L_STATUS_13 0x234
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#define GRL_L_STATUS_14 0x238
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#define GRL_L_STATUS_15 0x23c
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#define GRL_L_STATUS_16 0x240
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#define GRL_L_STATUS_17 0x244
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#define GRL_L_STATUS_18 0x248
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#define GRL_L_STATUS_19 0x24c
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#define GRL_L_STATUS_20 0x250
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#define GRL_L_STATUS_21 0x254
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#define GRL_L_STATUS_22 0x258
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#define GRL_L_STATUS_23 0x25c
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#define GRL_R_STATUS_0 0x260
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#define GRL_R_STATUS_1 0x264
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#define GRL_R_STATUS_2 0x268
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#define GRL_R_STATUS_3 0x26c
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#define GRL_R_STATUS_4 0x270
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#define GRL_R_STATUS_5 0x274
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#define GRL_R_STATUS_6 0x278
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#define GRL_R_STATUS_7 0x27c
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#define GRL_R_STATUS_8 0x280
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#define GRL_R_STATUS_9 0x284
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#define GRL_R_STATUS_10 0x288
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#define GRL_R_STATUS_11 0x28c
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#define GRL_R_STATUS_12 0x290
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#define GRL_R_STATUS_13 0x294
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#define GRL_R_STATUS_14 0x298
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#define GRL_R_STATUS_15 0x29c
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#define GRL_R_STATUS_16 0x2a0
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#define GRL_R_STATUS_17 0x2a4
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#define GRL_R_STATUS_18 0x2a8
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#define GRL_R_STATUS_19 0x2ac
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#define GRL_R_STATUS_20 0x2b0
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#define GRL_R_STATUS_21 0x2b4
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#define GRL_R_STATUS_22 0x2b8
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#define GRL_R_STATUS_23 0x2bc
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#define GRL_ABIST_CTRL0 0x2D4
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#define GRL_ABIST_CTRL1 0x2D8
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#define ABIST_EN BIT(7)
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#define ABIST_DATA_FMT (0x7 << 0)
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#define VIDEO_CFG_0 0x380
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#define VIDEO_CFG_1 0x384
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#define VIDEO_CFG_2 0x388
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#define VIDEO_CFG_3 0x38c
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#define VIDEO_CFG_4 0x390
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#define VIDEO_SOURCE_SEL BIT(7)
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#define NORMAL_PATH (1 << 7)
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#define GEN_RGB (0 << 7)
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#define HDMI_SYS_CFG1C 0x000
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#define HDMI_ON BIT(0)
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#define HDMI_RST BIT(1)
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#define ANLG_ON BIT(2)
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#define CFG10_DVI BIT(3)
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#define HDMI_TST BIT(3)
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#define SYS_KEYMASK1 (0xff << 8)
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#define SYS_KEYMASK2 (0xff << 16)
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#define AUD_OUTSYNC_EN BIT(24)
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#define AUD_OUTSYNC_PRE_EN BIT(25)
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#define I2CM_ON BIT(26)
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#define E2PROM_TYPE_8BIT BIT(27)
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#define MCM_E2PROM_ON BIT(28)
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#define EXT_E2PROM_ON BIT(29)
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#define HTPLG_PIN_SEL_OFF BIT(30)
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#define AES_EFUSE_ENABLE BIT(31)
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#define HDMI_SYS_CFG20 0x004
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#define DEEP_COLOR_MODE_MASK (3 << 1)
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#define COLOR_8BIT_MODE (0 << 1)
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#define COLOR_10BIT_MODE (1 << 1)
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#define COLOR_12BIT_MODE (2 << 1)
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#define COLOR_16BIT_MODE (3 << 1)
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#define DEEP_COLOR_EN BIT(0)
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#define HDMI_AUDIO_TEST_SEL BIT(8)
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#define HDMI2P0_EN BIT(11)
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#define HDMI_OUT_FIFO_EN BIT(16)
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#define HDMI_OUT_FIFO_CLK_INV BIT(17)
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#define MHL_MODE_ON BIT(28)
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#define MHL_PP_MODE BIT(29)
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#define MHL_SYNC_AUTO_EN BIT(30)
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#define HDMI_PCLK_FREE_RUN BIT(31)
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#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001
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#endif
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