Florian Fainelli 2be17eca48 ARM: dts: bcm2711: Fix PCIe interrupts ... [ Upstream commit 98481f3d72 ] The PCIe host bridge has two interrupt lines, one that goes towards it PCIE_INTR2 second level interrupt controller and one for its MSI second level interrupt controller. The first interrupt line is not currently managed by the driver, which is why it was not a functional problem. The interrupt-map property was also only listing the PCI_INTA interrupts when there are also the INTB, C and D. Reported-by: Jim Quinlan <jim2101024@gmail.com> Fixes: d5c8dc0d4c ("ARM: dts: bcm2711: Enable PCIe controller") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2021-12-01 09:19:03 +01:00
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arm	ARM: dts: bcm2711: Fix PCIe interrupts	2021-12-01 09:19:03 +01:00
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