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![Marcin Wojtas](/assets/img/avatar_default.png)
Armada 3700 SoC comprise a single XOR engine compliant with the ones used in older Marvell SoC's like Armada XP or 38x. The only thing that needs modification is the Mbus configuration, which has to be done on two levels: global and in device. The first one is inherited from the bootloader. The latter can be opened in a default way, leaving arbitration to the bus controller. Hence filled mbus_dram_target_info structure is not needed. Patch "dmaengine: mv_xor: optimize performance by using a subset of the XOR channels" introduced limitation for using XOR engines and channels vs number of available CPU's. Those constraints do not however fit Armada 3700 architecture with two possible CPU's and single, dual-channel engine. Hence in this commit an adjustment for setting maximum available channels is added. This patch enables XOR access to DRAM by opening default window to 4GB space with specific attribute. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
1377 lines
35 KiB
C
1377 lines
35 KiB
C
/*
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* offload engine driver for the Marvell XOR engine
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* Copyright (C) 2007, 2008, Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/memory.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/cpumask.h>
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#include <linux/platform_data/dma-mv_xor.h>
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#include "dmaengine.h"
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#include "mv_xor.h"
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enum mv_xor_type {
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XOR_ORION,
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XOR_ARMADA_38X,
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XOR_ARMADA_37XX,
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};
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enum mv_xor_mode {
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XOR_MODE_IN_REG,
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XOR_MODE_IN_DESC,
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};
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static void mv_xor_issue_pending(struct dma_chan *chan);
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#define to_mv_xor_chan(chan) \
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container_of(chan, struct mv_xor_chan, dmachan)
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#define to_mv_xor_slot(tx) \
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container_of(tx, struct mv_xor_desc_slot, async_tx)
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#define mv_chan_to_devp(chan) \
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((chan)->dmadev.dev)
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static void mv_desc_init(struct mv_xor_desc_slot *desc,
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dma_addr_t addr, u32 byte_count,
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enum dma_ctrl_flags flags)
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{
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struct mv_xor_desc *hw_desc = desc->hw_desc;
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hw_desc->status = XOR_DESC_DMA_OWNED;
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hw_desc->phy_next_desc = 0;
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/* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */
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hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ?
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XOR_DESC_EOD_INT_EN : 0;
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hw_desc->phy_dest_addr = addr;
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hw_desc->byte_count = byte_count;
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}
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static void mv_desc_set_mode(struct mv_xor_desc_slot *desc)
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{
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struct mv_xor_desc *hw_desc = desc->hw_desc;
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switch (desc->type) {
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case DMA_XOR:
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case DMA_INTERRUPT:
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hw_desc->desc_command |= XOR_DESC_OPERATION_XOR;
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break;
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case DMA_MEMCPY:
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hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY;
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break;
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default:
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BUG();
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return;
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}
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}
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static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
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u32 next_desc_addr)
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{
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struct mv_xor_desc *hw_desc = desc->hw_desc;
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BUG_ON(hw_desc->phy_next_desc);
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hw_desc->phy_next_desc = next_desc_addr;
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}
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static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
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int index, dma_addr_t addr)
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{
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struct mv_xor_desc *hw_desc = desc->hw_desc;
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hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
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if (desc->type == DMA_XOR)
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hw_desc->desc_command |= (1 << index);
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}
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static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
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{
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return readl_relaxed(XOR_CURR_DESC(chan));
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}
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static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
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u32 next_desc_addr)
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{
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writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
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}
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static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
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{
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u32 val = readl_relaxed(XOR_INTR_MASK(chan));
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val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
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writel_relaxed(val, XOR_INTR_MASK(chan));
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}
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static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
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{
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u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
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intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
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return intr_cause;
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}
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static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan)
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{
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u32 val;
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val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED;
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val = ~(val << (chan->idx * 16));
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dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
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writel_relaxed(val, XOR_INTR_CAUSE(chan));
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}
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static void mv_chan_clear_err_status(struct mv_xor_chan *chan)
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{
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u32 val = 0xFFFF0000 >> (chan->idx * 16);
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writel_relaxed(val, XOR_INTR_CAUSE(chan));
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}
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static void mv_chan_set_mode(struct mv_xor_chan *chan,
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u32 op_mode)
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{
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u32 config = readl_relaxed(XOR_CONFIG(chan));
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config &= ~0x7;
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config |= op_mode;
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#if defined(__BIG_ENDIAN)
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config |= XOR_DESCRIPTOR_SWAP;
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#else
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config &= ~XOR_DESCRIPTOR_SWAP;
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#endif
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writel_relaxed(config, XOR_CONFIG(chan));
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}
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static void mv_chan_activate(struct mv_xor_chan *chan)
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{
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dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
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/* writel ensures all descriptors are flushed before activation */
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writel(BIT(0), XOR_ACTIVATION(chan));
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}
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static char mv_chan_is_busy(struct mv_xor_chan *chan)
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{
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u32 state = readl_relaxed(XOR_ACTIVATION(chan));
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state = (state >> 4) & 0x3;
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return (state == 1) ? 1 : 0;
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}
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/*
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* mv_chan_start_new_chain - program the engine to operate on new
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* chain headed by sw_desc
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* Caller must hold &mv_chan->lock while calling this function
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*/
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static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan,
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struct mv_xor_desc_slot *sw_desc)
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{
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dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
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__func__, __LINE__, sw_desc);
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/* set the hardware chain */
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mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
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mv_chan->pending++;
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mv_xor_issue_pending(&mv_chan->dmachan);
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}
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static dma_cookie_t
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mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
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struct mv_xor_chan *mv_chan,
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dma_cookie_t cookie)
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{
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BUG_ON(desc->async_tx.cookie < 0);
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if (desc->async_tx.cookie > 0) {
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cookie = desc->async_tx.cookie;
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/* call the callback (must not sleep or submit new
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* operations to this channel)
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*/
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if (desc->async_tx.callback)
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desc->async_tx.callback(
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desc->async_tx.callback_param);
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dma_descriptor_unmap(&desc->async_tx);
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}
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/* run dependent operations */
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dma_run_dependencies(&desc->async_tx);
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return cookie;
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}
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static int
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mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan)
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{
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struct mv_xor_desc_slot *iter, *_iter;
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dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
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list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
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node) {
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if (async_tx_test_ack(&iter->async_tx))
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list_move_tail(&iter->node, &mv_chan->free_slots);
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}
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return 0;
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}
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static int
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mv_desc_clean_slot(struct mv_xor_desc_slot *desc,
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struct mv_xor_chan *mv_chan)
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{
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dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
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__func__, __LINE__, desc, desc->async_tx.flags);
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/* the client is allowed to attach dependent operations
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* until 'ack' is set
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*/
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if (!async_tx_test_ack(&desc->async_tx))
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/* move this slot to the completed_slots */
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list_move_tail(&desc->node, &mv_chan->completed_slots);
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else
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list_move_tail(&desc->node, &mv_chan->free_slots);
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return 0;
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}
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/* This function must be called with the mv_xor_chan spinlock held */
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static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan)
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{
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struct mv_xor_desc_slot *iter, *_iter;
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dma_cookie_t cookie = 0;
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int busy = mv_chan_is_busy(mv_chan);
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u32 current_desc = mv_chan_get_current_desc(mv_chan);
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int current_cleaned = 0;
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struct mv_xor_desc *hw_desc;
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dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
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dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
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mv_chan_clean_completed_slots(mv_chan);
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/* free completed slots from the chain starting with
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* the oldest descriptor
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*/
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list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
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node) {
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/* clean finished descriptors */
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hw_desc = iter->hw_desc;
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if (hw_desc->status & XOR_DESC_SUCCESS) {
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cookie = mv_desc_run_tx_complete_actions(iter, mv_chan,
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cookie);
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/* done processing desc, clean slot */
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mv_desc_clean_slot(iter, mv_chan);
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/* break if we did cleaned the current */
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if (iter->async_tx.phys == current_desc) {
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current_cleaned = 1;
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break;
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}
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} else {
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if (iter->async_tx.phys == current_desc) {
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current_cleaned = 0;
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break;
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}
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}
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}
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if ((busy == 0) && !list_empty(&mv_chan->chain)) {
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if (current_cleaned) {
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/*
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* current descriptor cleaned and removed, run
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* from list head
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*/
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iter = list_entry(mv_chan->chain.next,
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struct mv_xor_desc_slot,
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node);
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mv_chan_start_new_chain(mv_chan, iter);
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} else {
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if (!list_is_last(&iter->node, &mv_chan->chain)) {
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/*
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* descriptors are still waiting after
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* current, trigger them
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*/
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iter = list_entry(iter->node.next,
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struct mv_xor_desc_slot,
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node);
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mv_chan_start_new_chain(mv_chan, iter);
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} else {
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/*
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* some descriptors are still waiting
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* to be cleaned
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*/
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tasklet_schedule(&mv_chan->irq_tasklet);
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}
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}
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}
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if (cookie > 0)
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mv_chan->dmachan.completed_cookie = cookie;
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}
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static void mv_xor_tasklet(unsigned long data)
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{
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struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
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spin_lock_bh(&chan->lock);
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mv_chan_slot_cleanup(chan);
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spin_unlock_bh(&chan->lock);
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}
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static struct mv_xor_desc_slot *
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mv_chan_alloc_slot(struct mv_xor_chan *mv_chan)
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{
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struct mv_xor_desc_slot *iter;
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spin_lock_bh(&mv_chan->lock);
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if (!list_empty(&mv_chan->free_slots)) {
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iter = list_first_entry(&mv_chan->free_slots,
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struct mv_xor_desc_slot,
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node);
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list_move_tail(&iter->node, &mv_chan->allocated_slots);
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spin_unlock_bh(&mv_chan->lock);
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/* pre-ack descriptor */
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async_tx_ack(&iter->async_tx);
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iter->async_tx.cookie = -EBUSY;
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return iter;
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}
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spin_unlock_bh(&mv_chan->lock);
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/* try to free some slots if the allocation fails */
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tasklet_schedule(&mv_chan->irq_tasklet);
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return NULL;
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}
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/************************ DMA engine API functions ****************************/
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static dma_cookie_t
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mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
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struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
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struct mv_xor_desc_slot *old_chain_tail;
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dma_cookie_t cookie;
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int new_hw_chain = 1;
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dev_dbg(mv_chan_to_devp(mv_chan),
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"%s sw_desc %p: async_tx %p\n",
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__func__, sw_desc, &sw_desc->async_tx);
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spin_lock_bh(&mv_chan->lock);
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cookie = dma_cookie_assign(tx);
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if (list_empty(&mv_chan->chain))
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list_move_tail(&sw_desc->node, &mv_chan->chain);
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else {
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new_hw_chain = 0;
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old_chain_tail = list_entry(mv_chan->chain.prev,
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struct mv_xor_desc_slot,
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node);
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list_move_tail(&sw_desc->node, &mv_chan->chain);
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dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n",
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&old_chain_tail->async_tx.phys);
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/* fix up the hardware chain */
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mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys);
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/* if the channel is not busy */
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if (!mv_chan_is_busy(mv_chan)) {
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u32 current_desc = mv_chan_get_current_desc(mv_chan);
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/*
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* and the curren desc is the end of the chain before
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* the append, then we need to start the channel
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*/
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if (current_desc == old_chain_tail->async_tx.phys)
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new_hw_chain = 1;
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}
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}
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if (new_hw_chain)
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mv_chan_start_new_chain(mv_chan, sw_desc);
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spin_unlock_bh(&mv_chan->lock);
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return cookie;
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}
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/* returns the number of allocated descriptors */
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static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
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{
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void *virt_desc;
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dma_addr_t dma_desc;
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int idx;
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struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
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struct mv_xor_desc_slot *slot = NULL;
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int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
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/* Allocate descriptor slots */
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idx = mv_chan->slots_allocated;
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while (idx < num_descs_in_pool) {
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slot = kzalloc(sizeof(*slot), GFP_KERNEL);
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if (!slot) {
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dev_info(mv_chan_to_devp(mv_chan),
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"channel only initialized %d descriptor slots",
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idx);
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break;
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}
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virt_desc = mv_chan->dma_desc_pool_virt;
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slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE;
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dma_async_tx_descriptor_init(&slot->async_tx, chan);
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slot->async_tx.tx_submit = mv_xor_tx_submit;
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INIT_LIST_HEAD(&slot->node);
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dma_desc = mv_chan->dma_desc_pool;
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slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE;
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slot->idx = idx++;
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spin_lock_bh(&mv_chan->lock);
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mv_chan->slots_allocated = idx;
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list_add_tail(&slot->node, &mv_chan->free_slots);
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spin_unlock_bh(&mv_chan->lock);
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}
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dev_dbg(mv_chan_to_devp(mv_chan),
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"allocated %d descriptor slots\n",
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mv_chan->slots_allocated);
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return mv_chan->slots_allocated ? : -ENOMEM;
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}
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static struct dma_async_tx_descriptor *
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mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
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unsigned int src_cnt, size_t len, unsigned long flags)
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{
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struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
struct mv_xor_desc_slot *sw_desc;
|
|
|
|
if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
|
|
return NULL;
|
|
|
|
BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
|
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan),
|
|
"%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
|
|
__func__, src_cnt, len, &dest, flags);
|
|
|
|
sw_desc = mv_chan_alloc_slot(mv_chan);
|
|
if (sw_desc) {
|
|
sw_desc->type = DMA_XOR;
|
|
sw_desc->async_tx.flags = flags;
|
|
mv_desc_init(sw_desc, dest, len, flags);
|
|
if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
|
|
mv_desc_set_mode(sw_desc);
|
|
while (src_cnt--)
|
|
mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]);
|
|
}
|
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan),
|
|
"%s sw_desc %p async_tx %p \n",
|
|
__func__, sw_desc, &sw_desc->async_tx);
|
|
return sw_desc ? &sw_desc->async_tx : NULL;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
|
size_t len, unsigned long flags)
|
|
{
|
|
/*
|
|
* A MEMCPY operation is identical to an XOR operation with only
|
|
* a single source address.
|
|
*/
|
|
return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
|
|
{
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
dma_addr_t src, dest;
|
|
size_t len;
|
|
|
|
src = mv_chan->dummy_src_addr;
|
|
dest = mv_chan->dummy_dst_addr;
|
|
len = MV_XOR_MIN_BYTE_COUNT;
|
|
|
|
/*
|
|
* We implement the DMA_INTERRUPT operation as a minimum sized
|
|
* XOR operation with a single dummy source address.
|
|
*/
|
|
return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
|
|
}
|
|
|
|
static void mv_xor_free_chan_resources(struct dma_chan *chan)
|
|
{
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
struct mv_xor_desc_slot *iter, *_iter;
|
|
int in_use_descs = 0;
|
|
|
|
spin_lock_bh(&mv_chan->lock);
|
|
|
|
mv_chan_slot_cleanup(mv_chan);
|
|
|
|
list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
|
|
node) {
|
|
in_use_descs++;
|
|
list_move_tail(&iter->node, &mv_chan->free_slots);
|
|
}
|
|
list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
|
|
node) {
|
|
in_use_descs++;
|
|
list_move_tail(&iter->node, &mv_chan->free_slots);
|
|
}
|
|
list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots,
|
|
node) {
|
|
in_use_descs++;
|
|
list_move_tail(&iter->node, &mv_chan->free_slots);
|
|
}
|
|
list_for_each_entry_safe_reverse(
|
|
iter, _iter, &mv_chan->free_slots, node) {
|
|
list_del(&iter->node);
|
|
kfree(iter);
|
|
mv_chan->slots_allocated--;
|
|
}
|
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
|
|
__func__, mv_chan->slots_allocated);
|
|
spin_unlock_bh(&mv_chan->lock);
|
|
|
|
if (in_use_descs)
|
|
dev_err(mv_chan_to_devp(mv_chan),
|
|
"freeing %d in use descriptors!\n", in_use_descs);
|
|
}
|
|
|
|
/**
|
|
* mv_xor_status - poll the status of an XOR transaction
|
|
* @chan: XOR channel handle
|
|
* @cookie: XOR transaction identifier
|
|
* @txstate: XOR transactions state holder (or NULL)
|
|
*/
|
|
static enum dma_status mv_xor_status(struct dma_chan *chan,
|
|
dma_cookie_t cookie,
|
|
struct dma_tx_state *txstate)
|
|
{
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
enum dma_status ret;
|
|
|
|
ret = dma_cookie_status(chan, cookie, txstate);
|
|
if (ret == DMA_COMPLETE)
|
|
return ret;
|
|
|
|
spin_lock_bh(&mv_chan->lock);
|
|
mv_chan_slot_cleanup(mv_chan);
|
|
spin_unlock_bh(&mv_chan->lock);
|
|
|
|
return dma_cookie_status(chan, cookie, txstate);
|
|
}
|
|
|
|
static void mv_chan_dump_regs(struct mv_xor_chan *chan)
|
|
{
|
|
u32 val;
|
|
|
|
val = readl_relaxed(XOR_CONFIG(chan));
|
|
dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val);
|
|
|
|
val = readl_relaxed(XOR_ACTIVATION(chan));
|
|
dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val);
|
|
|
|
val = readl_relaxed(XOR_INTR_CAUSE(chan));
|
|
dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val);
|
|
|
|
val = readl_relaxed(XOR_INTR_MASK(chan));
|
|
dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val);
|
|
|
|
val = readl_relaxed(XOR_ERROR_CAUSE(chan));
|
|
dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val);
|
|
|
|
val = readl_relaxed(XOR_ERROR_ADDR(chan));
|
|
dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val);
|
|
}
|
|
|
|
static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan,
|
|
u32 intr_cause)
|
|
{
|
|
if (intr_cause & XOR_INT_ERR_DECODE) {
|
|
dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n");
|
|
return;
|
|
}
|
|
|
|
dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n",
|
|
chan->idx, intr_cause);
|
|
|
|
mv_chan_dump_regs(chan);
|
|
WARN_ON(1);
|
|
}
|
|
|
|
static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
|
|
{
|
|
struct mv_xor_chan *chan = data;
|
|
u32 intr_cause = mv_chan_get_intr_cause(chan);
|
|
|
|
dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
|
|
|
|
if (intr_cause & XOR_INTR_ERRORS)
|
|
mv_chan_err_interrupt_handler(chan, intr_cause);
|
|
|
|
tasklet_schedule(&chan->irq_tasklet);
|
|
|
|
mv_chan_clear_eoc_cause(chan);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void mv_xor_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
|
|
if (mv_chan->pending >= MV_XOR_THRESHOLD) {
|
|
mv_chan->pending = 0;
|
|
mv_chan_activate(mv_chan);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Perform a transaction to verify the HW works.
|
|
*/
|
|
|
|
static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan)
|
|
{
|
|
int i, ret;
|
|
void *src, *dest;
|
|
dma_addr_t src_dma, dest_dma;
|
|
struct dma_chan *dma_chan;
|
|
dma_cookie_t cookie;
|
|
struct dma_async_tx_descriptor *tx;
|
|
struct dmaengine_unmap_data *unmap;
|
|
int err = 0;
|
|
|
|
src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
|
|
if (!src)
|
|
return -ENOMEM;
|
|
|
|
dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
|
|
if (!dest) {
|
|
kfree(src);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Fill in src buffer */
|
|
for (i = 0; i < PAGE_SIZE; i++)
|
|
((u8 *) src)[i] = (u8)i;
|
|
|
|
dma_chan = &mv_chan->dmachan;
|
|
if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
|
|
err = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL);
|
|
if (!unmap) {
|
|
err = -ENOMEM;
|
|
goto free_resources;
|
|
}
|
|
|
|
src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0,
|
|
PAGE_SIZE, DMA_TO_DEVICE);
|
|
unmap->addr[0] = src_dma;
|
|
|
|
ret = dma_mapping_error(dma_chan->device->dev, src_dma);
|
|
if (ret) {
|
|
err = -ENOMEM;
|
|
goto free_resources;
|
|
}
|
|
unmap->to_cnt = 1;
|
|
|
|
dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0,
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
|
unmap->addr[1] = dest_dma;
|
|
|
|
ret = dma_mapping_error(dma_chan->device->dev, dest_dma);
|
|
if (ret) {
|
|
err = -ENOMEM;
|
|
goto free_resources;
|
|
}
|
|
unmap->from_cnt = 1;
|
|
unmap->len = PAGE_SIZE;
|
|
|
|
tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
|
|
PAGE_SIZE, 0);
|
|
if (!tx) {
|
|
dev_err(dma_chan->device->dev,
|
|
"Self-test cannot prepare operation, disabling\n");
|
|
err = -ENODEV;
|
|
goto free_resources;
|
|
}
|
|
|
|
cookie = mv_xor_tx_submit(tx);
|
|
if (dma_submit_error(cookie)) {
|
|
dev_err(dma_chan->device->dev,
|
|
"Self-test submit error, disabling\n");
|
|
err = -ENODEV;
|
|
goto free_resources;
|
|
}
|
|
|
|
mv_xor_issue_pending(dma_chan);
|
|
async_tx_ack(tx);
|
|
msleep(1);
|
|
|
|
if (mv_xor_status(dma_chan, cookie, NULL) !=
|
|
DMA_COMPLETE) {
|
|
dev_err(dma_chan->device->dev,
|
|
"Self-test copy timed out, disabling\n");
|
|
err = -ENODEV;
|
|
goto free_resources;
|
|
}
|
|
|
|
dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
|
if (memcmp(src, dest, PAGE_SIZE)) {
|
|
dev_err(dma_chan->device->dev,
|
|
"Self-test copy failed compare, disabling\n");
|
|
err = -ENODEV;
|
|
goto free_resources;
|
|
}
|
|
|
|
free_resources:
|
|
dmaengine_unmap_put(unmap);
|
|
mv_xor_free_chan_resources(dma_chan);
|
|
out:
|
|
kfree(src);
|
|
kfree(dest);
|
|
return err;
|
|
}
|
|
|
|
#define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
|
|
static int
|
|
mv_chan_xor_self_test(struct mv_xor_chan *mv_chan)
|
|
{
|
|
int i, src_idx, ret;
|
|
struct page *dest;
|
|
struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
|
|
dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
|
|
dma_addr_t dest_dma;
|
|
struct dma_async_tx_descriptor *tx;
|
|
struct dmaengine_unmap_data *unmap;
|
|
struct dma_chan *dma_chan;
|
|
dma_cookie_t cookie;
|
|
u8 cmp_byte = 0;
|
|
u32 cmp_word;
|
|
int err = 0;
|
|
int src_count = MV_XOR_NUM_SRC_TEST;
|
|
|
|
for (src_idx = 0; src_idx < src_count; src_idx++) {
|
|
xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
|
|
if (!xor_srcs[src_idx]) {
|
|
while (src_idx--)
|
|
__free_page(xor_srcs[src_idx]);
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
dest = alloc_page(GFP_KERNEL);
|
|
if (!dest) {
|
|
while (src_idx--)
|
|
__free_page(xor_srcs[src_idx]);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Fill in src buffers */
|
|
for (src_idx = 0; src_idx < src_count; src_idx++) {
|
|
u8 *ptr = page_address(xor_srcs[src_idx]);
|
|
for (i = 0; i < PAGE_SIZE; i++)
|
|
ptr[i] = (1 << src_idx);
|
|
}
|
|
|
|
for (src_idx = 0; src_idx < src_count; src_idx++)
|
|
cmp_byte ^= (u8) (1 << src_idx);
|
|
|
|
cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
|
|
(cmp_byte << 8) | cmp_byte;
|
|
|
|
memset(page_address(dest), 0, PAGE_SIZE);
|
|
|
|
dma_chan = &mv_chan->dmachan;
|
|
if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
|
|
err = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1,
|
|
GFP_KERNEL);
|
|
if (!unmap) {
|
|
err = -ENOMEM;
|
|
goto free_resources;
|
|
}
|
|
|
|
/* test xor */
|
|
for (i = 0; i < src_count; i++) {
|
|
unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
|
|
0, PAGE_SIZE, DMA_TO_DEVICE);
|
|
dma_srcs[i] = unmap->addr[i];
|
|
ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]);
|
|
if (ret) {
|
|
err = -ENOMEM;
|
|
goto free_resources;
|
|
}
|
|
unmap->to_cnt++;
|
|
}
|
|
|
|
unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
|
|
DMA_FROM_DEVICE);
|
|
dest_dma = unmap->addr[src_count];
|
|
ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]);
|
|
if (ret) {
|
|
err = -ENOMEM;
|
|
goto free_resources;
|
|
}
|
|
unmap->from_cnt = 1;
|
|
unmap->len = PAGE_SIZE;
|
|
|
|
tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
|
|
src_count, PAGE_SIZE, 0);
|
|
if (!tx) {
|
|
dev_err(dma_chan->device->dev,
|
|
"Self-test cannot prepare operation, disabling\n");
|
|
err = -ENODEV;
|
|
goto free_resources;
|
|
}
|
|
|
|
cookie = mv_xor_tx_submit(tx);
|
|
if (dma_submit_error(cookie)) {
|
|
dev_err(dma_chan->device->dev,
|
|
"Self-test submit error, disabling\n");
|
|
err = -ENODEV;
|
|
goto free_resources;
|
|
}
|
|
|
|
mv_xor_issue_pending(dma_chan);
|
|
async_tx_ack(tx);
|
|
msleep(8);
|
|
|
|
if (mv_xor_status(dma_chan, cookie, NULL) !=
|
|
DMA_COMPLETE) {
|
|
dev_err(dma_chan->device->dev,
|
|
"Self-test xor timed out, disabling\n");
|
|
err = -ENODEV;
|
|
goto free_resources;
|
|
}
|
|
|
|
dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
|
for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
|
|
u32 *ptr = page_address(dest);
|
|
if (ptr[i] != cmp_word) {
|
|
dev_err(dma_chan->device->dev,
|
|
"Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
|
|
i, ptr[i], cmp_word);
|
|
err = -ENODEV;
|
|
goto free_resources;
|
|
}
|
|
}
|
|
|
|
free_resources:
|
|
dmaengine_unmap_put(unmap);
|
|
mv_xor_free_chan_resources(dma_chan);
|
|
out:
|
|
src_idx = src_count;
|
|
while (src_idx--)
|
|
__free_page(xor_srcs[src_idx]);
|
|
__free_page(dest);
|
|
return err;
|
|
}
|
|
|
|
static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
|
|
{
|
|
struct dma_chan *chan, *_chan;
|
|
struct device *dev = mv_chan->dmadev.dev;
|
|
|
|
dma_async_device_unregister(&mv_chan->dmadev);
|
|
|
|
dma_free_coherent(dev, MV_XOR_POOL_SIZE,
|
|
mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
|
|
dma_unmap_single(dev, mv_chan->dummy_src_addr,
|
|
MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
|
|
dma_unmap_single(dev, mv_chan->dummy_dst_addr,
|
|
MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
|
|
|
|
list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
|
|
device_node) {
|
|
list_del(&chan->device_node);
|
|
}
|
|
|
|
free_irq(mv_chan->irq, mv_chan);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct mv_xor_chan *
|
|
mv_xor_channel_add(struct mv_xor_device *xordev,
|
|
struct platform_device *pdev,
|
|
int idx, dma_cap_mask_t cap_mask, int irq)
|
|
{
|
|
int ret = 0;
|
|
struct mv_xor_chan *mv_chan;
|
|
struct dma_device *dma_dev;
|
|
|
|
mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
|
|
if (!mv_chan)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
mv_chan->idx = idx;
|
|
mv_chan->irq = irq;
|
|
if (xordev->xor_type == XOR_ORION)
|
|
mv_chan->op_in_desc = XOR_MODE_IN_REG;
|
|
else
|
|
mv_chan->op_in_desc = XOR_MODE_IN_DESC;
|
|
|
|
dma_dev = &mv_chan->dmadev;
|
|
|
|
/*
|
|
* These source and destination dummy buffers are used to implement
|
|
* a DMA_INTERRUPT operation as a minimum-sized XOR operation.
|
|
* Hence, we only need to map the buffers at initialization-time.
|
|
*/
|
|
mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev,
|
|
mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
|
|
mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev,
|
|
mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
|
|
|
|
/* allocate coherent memory for hardware descriptors
|
|
* note: writecombine gives slightly better performance, but
|
|
* requires that we explicitly flush the writes
|
|
*/
|
|
mv_chan->dma_desc_pool_virt =
|
|
dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool,
|
|
GFP_KERNEL);
|
|
if (!mv_chan->dma_desc_pool_virt)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
/* discover transaction capabilites from the platform data */
|
|
dma_dev->cap_mask = cap_mask;
|
|
|
|
INIT_LIST_HEAD(&dma_dev->channels);
|
|
|
|
/* set base routines */
|
|
dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
|
|
dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
|
|
dma_dev->device_tx_status = mv_xor_status;
|
|
dma_dev->device_issue_pending = mv_xor_issue_pending;
|
|
dma_dev->dev = &pdev->dev;
|
|
|
|
/* set prep routines based on capability */
|
|
if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
|
|
dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt;
|
|
if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
|
|
dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
|
|
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
|
|
dma_dev->max_xor = 8;
|
|
dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
|
|
}
|
|
|
|
mv_chan->mmr_base = xordev->xor_base;
|
|
mv_chan->mmr_high_base = xordev->xor_high_base;
|
|
tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
|
|
mv_chan);
|
|
|
|
/* clear errors before enabling interrupts */
|
|
mv_chan_clear_err_status(mv_chan);
|
|
|
|
ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
|
|
0, dev_name(&pdev->dev), mv_chan);
|
|
if (ret)
|
|
goto err_free_dma;
|
|
|
|
mv_chan_unmask_interrupts(mv_chan);
|
|
|
|
if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
|
|
mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC);
|
|
else
|
|
mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR);
|
|
|
|
spin_lock_init(&mv_chan->lock);
|
|
INIT_LIST_HEAD(&mv_chan->chain);
|
|
INIT_LIST_HEAD(&mv_chan->completed_slots);
|
|
INIT_LIST_HEAD(&mv_chan->free_slots);
|
|
INIT_LIST_HEAD(&mv_chan->allocated_slots);
|
|
mv_chan->dmachan.device = dma_dev;
|
|
dma_cookie_init(&mv_chan->dmachan);
|
|
|
|
list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
|
|
|
|
if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
|
|
ret = mv_chan_memcpy_self_test(mv_chan);
|
|
dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
|
|
if (ret)
|
|
goto err_free_irq;
|
|
}
|
|
|
|
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
|
|
ret = mv_chan_xor_self_test(mv_chan);
|
|
dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
|
|
if (ret)
|
|
goto err_free_irq;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n",
|
|
mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode",
|
|
dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
|
|
dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
|
|
dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
|
|
|
|
dma_async_device_register(dma_dev);
|
|
return mv_chan;
|
|
|
|
err_free_irq:
|
|
free_irq(mv_chan->irq, mv_chan);
|
|
err_free_dma:
|
|
dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
|
|
mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
static void
|
|
mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
|
|
const struct mbus_dram_target_info *dram)
|
|
{
|
|
void __iomem *base = xordev->xor_high_base;
|
|
u32 win_enable = 0;
|
|
int i;
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
writel(0, base + WINDOW_BASE(i));
|
|
writel(0, base + WINDOW_SIZE(i));
|
|
if (i < 4)
|
|
writel(0, base + WINDOW_REMAP_HIGH(i));
|
|
}
|
|
|
|
for (i = 0; i < dram->num_cs; i++) {
|
|
const struct mbus_dram_window *cs = dram->cs + i;
|
|
|
|
writel((cs->base & 0xffff0000) |
|
|
(cs->mbus_attr << 8) |
|
|
dram->mbus_dram_target_id, base + WINDOW_BASE(i));
|
|
writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
|
|
|
|
win_enable |= (1 << i);
|
|
win_enable |= 3 << (16 + (2 * i));
|
|
}
|
|
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(0));
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(1));
|
|
writel(0, base + WINDOW_OVERRIDE_CTRL(0));
|
|
writel(0, base + WINDOW_OVERRIDE_CTRL(1));
|
|
}
|
|
|
|
static void
|
|
mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev)
|
|
{
|
|
void __iomem *base = xordev->xor_high_base;
|
|
u32 win_enable = 0;
|
|
int i;
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
writel(0, base + WINDOW_BASE(i));
|
|
writel(0, base + WINDOW_SIZE(i));
|
|
if (i < 4)
|
|
writel(0, base + WINDOW_REMAP_HIGH(i));
|
|
}
|
|
/*
|
|
* For Armada3700 open default 4GB Mbus window. The dram
|
|
* related configuration are done at AXIS level.
|
|
*/
|
|
writel(0xffff0000, base + WINDOW_SIZE(0));
|
|
win_enable |= 1;
|
|
win_enable |= 3 << 16;
|
|
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(0));
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(1));
|
|
writel(0, base + WINDOW_OVERRIDE_CTRL(0));
|
|
writel(0, base + WINDOW_OVERRIDE_CTRL(1));
|
|
}
|
|
|
|
/*
|
|
* Since this XOR driver is basically used only for RAID5, we don't
|
|
* need to care about synchronizing ->suspend with DMA activity,
|
|
* because the DMA engine will naturally be quiet due to the block
|
|
* devices being suspended.
|
|
*/
|
|
static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct mv_xor_device *xordev = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
|
|
struct mv_xor_chan *mv_chan = xordev->channels[i];
|
|
|
|
if (!mv_chan)
|
|
continue;
|
|
|
|
mv_chan->saved_config_reg =
|
|
readl_relaxed(XOR_CONFIG(mv_chan));
|
|
mv_chan->saved_int_mask_reg =
|
|
readl_relaxed(XOR_INTR_MASK(mv_chan));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mv_xor_resume(struct platform_device *dev)
|
|
{
|
|
struct mv_xor_device *xordev = platform_get_drvdata(dev);
|
|
const struct mbus_dram_target_info *dram;
|
|
int i;
|
|
|
|
for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
|
|
struct mv_xor_chan *mv_chan = xordev->channels[i];
|
|
|
|
if (!mv_chan)
|
|
continue;
|
|
|
|
writel_relaxed(mv_chan->saved_config_reg,
|
|
XOR_CONFIG(mv_chan));
|
|
writel_relaxed(mv_chan->saved_int_mask_reg,
|
|
XOR_INTR_MASK(mv_chan));
|
|
}
|
|
|
|
if (xordev->xor_type == XOR_ARMADA_37XX) {
|
|
mv_xor_conf_mbus_windows_a3700(xordev);
|
|
return 0;
|
|
}
|
|
|
|
dram = mv_mbus_dram_info();
|
|
if (dram)
|
|
mv_xor_conf_mbus_windows(xordev, dram);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mv_xor_dt_ids[] = {
|
|
{ .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION },
|
|
{ .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X },
|
|
{ .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX },
|
|
{},
|
|
};
|
|
|
|
static unsigned int mv_xor_engine_count;
|
|
|
|
static int mv_xor_probe(struct platform_device *pdev)
|
|
{
|
|
const struct mbus_dram_target_info *dram;
|
|
struct mv_xor_device *xordev;
|
|
struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
|
struct resource *res;
|
|
unsigned int max_engines, max_channels;
|
|
int i, ret;
|
|
|
|
dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
|
|
|
|
xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
|
|
if (!xordev)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENODEV;
|
|
|
|
xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
|
|
resource_size(res));
|
|
if (!xordev->xor_base)
|
|
return -EBUSY;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
if (!res)
|
|
return -ENODEV;
|
|
|
|
xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
|
|
resource_size(res));
|
|
if (!xordev->xor_high_base)
|
|
return -EBUSY;
|
|
|
|
platform_set_drvdata(pdev, xordev);
|
|
|
|
|
|
/*
|
|
* We need to know which type of XOR device we use before
|
|
* setting up. In non-dt case it can only be the legacy one.
|
|
*/
|
|
xordev->xor_type = XOR_ORION;
|
|
if (pdev->dev.of_node) {
|
|
const struct of_device_id *of_id =
|
|
of_match_device(mv_xor_dt_ids,
|
|
&pdev->dev);
|
|
|
|
xordev->xor_type = (uintptr_t)of_id->data;
|
|
}
|
|
|
|
/*
|
|
* (Re-)program MBUS remapping windows if we are asked to.
|
|
*/
|
|
if (xordev->xor_type == XOR_ARMADA_37XX) {
|
|
mv_xor_conf_mbus_windows_a3700(xordev);
|
|
} else {
|
|
dram = mv_mbus_dram_info();
|
|
if (dram)
|
|
mv_xor_conf_mbus_windows(xordev, dram);
|
|
}
|
|
|
|
/* Not all platforms can gate the clock, so it is not
|
|
* an error if the clock does not exists.
|
|
*/
|
|
xordev->clk = clk_get(&pdev->dev, NULL);
|
|
if (!IS_ERR(xordev->clk))
|
|
clk_prepare_enable(xordev->clk);
|
|
|
|
/*
|
|
* We don't want to have more than one channel per CPU in
|
|
* order for async_tx to perform well. So we limit the number
|
|
* of engines and channels so that we take into account this
|
|
* constraint. Note that we also want to use channels from
|
|
* separate engines when possible. For dual-CPU Armada 3700
|
|
* SoC with single XOR engine allow using its both channels.
|
|
*/
|
|
max_engines = num_present_cpus();
|
|
if (xordev->xor_type == XOR_ARMADA_37XX)
|
|
max_channels = num_present_cpus();
|
|
else
|
|
max_channels = min_t(unsigned int,
|
|
MV_XOR_MAX_CHANNELS,
|
|
DIV_ROUND_UP(num_present_cpus(), 2));
|
|
|
|
if (mv_xor_engine_count >= max_engines)
|
|
return 0;
|
|
|
|
if (pdev->dev.of_node) {
|
|
struct device_node *np;
|
|
int i = 0;
|
|
|
|
for_each_child_of_node(pdev->dev.of_node, np) {
|
|
struct mv_xor_chan *chan;
|
|
dma_cap_mask_t cap_mask;
|
|
int irq;
|
|
|
|
if (i >= max_channels)
|
|
continue;
|
|
|
|
dma_cap_zero(cap_mask);
|
|
dma_cap_set(DMA_MEMCPY, cap_mask);
|
|
dma_cap_set(DMA_XOR, cap_mask);
|
|
dma_cap_set(DMA_INTERRUPT, cap_mask);
|
|
|
|
irq = irq_of_parse_and_map(np, 0);
|
|
if (!irq) {
|
|
ret = -ENODEV;
|
|
goto err_channel_add;
|
|
}
|
|
|
|
chan = mv_xor_channel_add(xordev, pdev, i,
|
|
cap_mask, irq);
|
|
if (IS_ERR(chan)) {
|
|
ret = PTR_ERR(chan);
|
|
irq_dispose_mapping(irq);
|
|
goto err_channel_add;
|
|
}
|
|
|
|
xordev->channels[i] = chan;
|
|
i++;
|
|
}
|
|
} else if (pdata && pdata->channels) {
|
|
for (i = 0; i < max_channels; i++) {
|
|
struct mv_xor_channel_data *cd;
|
|
struct mv_xor_chan *chan;
|
|
int irq;
|
|
|
|
cd = &pdata->channels[i];
|
|
if (!cd) {
|
|
ret = -ENODEV;
|
|
goto err_channel_add;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, i);
|
|
if (irq < 0) {
|
|
ret = irq;
|
|
goto err_channel_add;
|
|
}
|
|
|
|
chan = mv_xor_channel_add(xordev, pdev, i,
|
|
cd->cap_mask, irq);
|
|
if (IS_ERR(chan)) {
|
|
ret = PTR_ERR(chan);
|
|
goto err_channel_add;
|
|
}
|
|
|
|
xordev->channels[i] = chan;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_channel_add:
|
|
for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
|
|
if (xordev->channels[i]) {
|
|
mv_xor_channel_remove(xordev->channels[i]);
|
|
if (pdev->dev.of_node)
|
|
irq_dispose_mapping(xordev->channels[i]->irq);
|
|
}
|
|
|
|
if (!IS_ERR(xordev->clk)) {
|
|
clk_disable_unprepare(xordev->clk);
|
|
clk_put(xordev->clk);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver mv_xor_driver = {
|
|
.probe = mv_xor_probe,
|
|
.suspend = mv_xor_suspend,
|
|
.resume = mv_xor_resume,
|
|
.driver = {
|
|
.name = MV_XOR_NAME,
|
|
.of_match_table = of_match_ptr(mv_xor_dt_ids),
|
|
},
|
|
};
|
|
|
|
|
|
static int __init mv_xor_init(void)
|
|
{
|
|
return platform_driver_register(&mv_xor_driver);
|
|
}
|
|
device_initcall(mv_xor_init);
|
|
|
|
/*
|
|
MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
|
|
MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
|
|
MODULE_LICENSE("GPL");
|
|
*/
|