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![Valentin Rothberg](/assets/img/avatar_default.png)
The IRQF_DISABLED flag is a NOOP and has been scheduled for removal since Linux v2.6.36 by commit6932bf37be
("genirq: Remove IRQF_DISABLED from core code"). According to commite58aa3d2d0
("genirq: Run irq handlers with interrupts disabled"), running IRQ handlers with interrupts enabled can cause stack overflows when the interrupt line of the issuing device is still active. This patch ends the grace period for IRQF_DISABLED (i.e., SA_INTERRUPT in older versions of Linux) and removes the definition and all remaining usages of this flag. There's still a few non-functional references left in the kernel source: - The bigger hunk in Documentation/scsi/ncr53c8xx.txt is removed entirely as IRQF_DISABLED is gone now; the usage in older kernel versions (including the old SA_INTERRUPT flag) should be discouraged. The trouble of using IRQF_SHARED is a general problem and not specific to any driver. - I left the reference in Documentation/PCI/MSI-HOWTO.txt untouched since it has already been removed in linux-next. - All remaining references are changelogs that I suggest to keep. Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com> Cc: Afzal Mohammed <afzal@ti.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Dan Carpenter <dan.carpenter@oracle.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Ewan Milne <emilne@redhat.com> Cc: Eyal Perry <eyalpe@mellanox.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Hannes Reinecke <hare@suse.de> Cc: Hongliang Tao <taohl@lemote.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Keerthy <j-keerthy@ti.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Nishanth Menon <nm@ti.com> Cc: Paul Bolle <pebolle@tiscali.nl> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Lambert <lambert.quentin@gmail.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Sricharan R <r.sricharan@ti.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Lindgren <tony@atomide.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: iss_storagedev@hp.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Link: http://lkml.kernel.org/r/1425565425-12604-1-git-send-email-valentinrothberg@gmail.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
890 lines
23 KiB
C
890 lines
23 KiB
C
/*
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* Hisilicon NAND Flash controller driver
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*
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* Copyright © 2012-2014 HiSilicon Technologies Co., Ltd.
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* http://www.hisilicon.com
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*
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* Author: Zhou Wang <wangzhou.bry@gmail.com>
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* The initial developer of the original code is Zhiyong Cai
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* <caizhiyong@huawei.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/of.h>
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#include <linux/of_mtd.h>
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#include <linux/mtd/mtd.h>
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#include <linux/sizes.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/mtd/nand.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/partitions.h>
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#define HINFC504_MAX_CHIP (4)
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#define HINFC504_W_LATCH (5)
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#define HINFC504_R_LATCH (7)
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#define HINFC504_RW_LATCH (3)
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#define HINFC504_NFC_TIMEOUT (2 * HZ)
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#define HINFC504_NFC_PM_TIMEOUT (1 * HZ)
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#define HINFC504_NFC_DMA_TIMEOUT (5 * HZ)
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#define HINFC504_CHIP_DELAY (25)
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#define HINFC504_REG_BASE_ADDRESS_LEN (0x100)
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#define HINFC504_BUFFER_BASE_ADDRESS_LEN (2048 + 128)
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#define HINFC504_ADDR_CYCLE_MASK 0x4
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#define HINFC504_CON 0x00
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#define HINFC504_CON_OP_MODE_NORMAL BIT(0)
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#define HINFC504_CON_PAGEISZE_SHIFT (1)
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#define HINFC504_CON_PAGESIZE_MASK (0x07)
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#define HINFC504_CON_BUS_WIDTH BIT(4)
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#define HINFC504_CON_READY_BUSY_SEL BIT(8)
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#define HINFC504_CON_ECCTYPE_SHIFT (9)
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#define HINFC504_CON_ECCTYPE_MASK (0x07)
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#define HINFC504_PWIDTH 0x04
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#define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) \
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((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8))
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#define HINFC504_CMD 0x0C
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#define HINFC504_ADDRL 0x10
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#define HINFC504_ADDRH 0x14
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#define HINFC504_DATA_NUM 0x18
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#define HINFC504_OP 0x1C
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#define HINFC504_OP_READ_DATA_EN BIT(1)
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#define HINFC504_OP_WAIT_READY_EN BIT(2)
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#define HINFC504_OP_CMD2_EN BIT(3)
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#define HINFC504_OP_WRITE_DATA_EN BIT(4)
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#define HINFC504_OP_ADDR_EN BIT(5)
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#define HINFC504_OP_CMD1_EN BIT(6)
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#define HINFC504_OP_NF_CS_SHIFT (7)
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#define HINFC504_OP_NF_CS_MASK (3)
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#define HINFC504_OP_ADDR_CYCLE_SHIFT (9)
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#define HINFC504_OP_ADDR_CYCLE_MASK (7)
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#define HINFC504_STATUS 0x20
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#define HINFC504_READY BIT(0)
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#define HINFC504_INTEN 0x24
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#define HINFC504_INTEN_DMA BIT(9)
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#define HINFC504_INTEN_UE BIT(6)
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#define HINFC504_INTEN_CE BIT(5)
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#define HINFC504_INTS 0x28
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#define HINFC504_INTS_DMA BIT(9)
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#define HINFC504_INTS_UE BIT(6)
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#define HINFC504_INTS_CE BIT(5)
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#define HINFC504_INTCLR 0x2C
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#define HINFC504_INTCLR_DMA BIT(9)
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#define HINFC504_INTCLR_UE BIT(6)
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#define HINFC504_INTCLR_CE BIT(5)
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#define HINFC504_ECC_STATUS 0x5C
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#define HINFC504_ECC_16_BIT_SHIFT 12
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#define HINFC504_DMA_CTRL 0x60
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#define HINFC504_DMA_CTRL_DMA_START BIT(0)
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#define HINFC504_DMA_CTRL_WE BIT(1)
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#define HINFC504_DMA_CTRL_DATA_AREA_EN BIT(2)
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#define HINFC504_DMA_CTRL_OOB_AREA_EN BIT(3)
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#define HINFC504_DMA_CTRL_BURST4_EN BIT(4)
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#define HINFC504_DMA_CTRL_BURST8_EN BIT(5)
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#define HINFC504_DMA_CTRL_BURST16_EN BIT(6)
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#define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT (7)
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#define HINFC504_DMA_CTRL_ADDR_NUM_MASK (1)
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#define HINFC504_DMA_CTRL_CS_SHIFT (8)
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#define HINFC504_DMA_CTRL_CS_MASK (0x03)
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#define HINFC504_DMA_ADDR_DATA 0x64
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#define HINFC504_DMA_ADDR_OOB 0x68
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#define HINFC504_DMA_LEN 0x6C
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#define HINFC504_DMA_LEN_OOB_SHIFT (16)
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#define HINFC504_DMA_LEN_OOB_MASK (0xFFF)
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#define HINFC504_DMA_PARA 0x70
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#define HINFC504_DMA_PARA_DATA_RW_EN BIT(0)
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#define HINFC504_DMA_PARA_OOB_RW_EN BIT(1)
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#define HINFC504_DMA_PARA_DATA_EDC_EN BIT(2)
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#define HINFC504_DMA_PARA_OOB_EDC_EN BIT(3)
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#define HINFC504_DMA_PARA_DATA_ECC_EN BIT(4)
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#define HINFC504_DMA_PARA_OOB_ECC_EN BIT(5)
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#define HINFC_VERSION 0x74
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#define HINFC504_LOG_READ_ADDR 0x7C
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#define HINFC504_LOG_READ_LEN 0x80
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#define HINFC504_NANDINFO_LEN 0x10
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struct hinfc_host {
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struct nand_chip chip;
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struct mtd_info mtd;
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struct device *dev;
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void __iomem *iobase;
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void __iomem *mmio;
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struct completion cmd_complete;
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unsigned int offset;
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unsigned int command;
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int chipselect;
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unsigned int addr_cycle;
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u32 addr_value[2];
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u32 cache_addr_value[2];
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char *buffer;
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dma_addr_t dma_buffer;
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dma_addr_t dma_oob;
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int version;
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unsigned int irq_status; /* interrupt status */
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};
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static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg)
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{
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return readl(host->iobase + reg);
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}
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static inline void hinfc_write(struct hinfc_host *host, unsigned int value,
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unsigned int reg)
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{
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writel(value, host->iobase + reg);
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}
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static void wait_controller_finished(struct hinfc_host *host)
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{
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unsigned long timeout = jiffies + HINFC504_NFC_TIMEOUT;
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int val;
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while (time_before(jiffies, timeout)) {
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val = hinfc_read(host, HINFC504_STATUS);
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if (host->command == NAND_CMD_ERASE2) {
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/* nfc is ready */
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while (!(val & HINFC504_READY)) {
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usleep_range(500, 1000);
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val = hinfc_read(host, HINFC504_STATUS);
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}
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return;
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}
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if (val & HINFC504_READY)
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return;
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}
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/* wait cmd timeout */
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dev_err(host->dev, "Wait NAND controller exec cmd timeout.\n");
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}
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static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev)
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{
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struct mtd_info *mtd = &host->mtd;
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struct nand_chip *chip = mtd->priv;
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unsigned long val;
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int ret;
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hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA);
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hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB);
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if (chip->ecc.mode == NAND_ECC_NONE) {
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hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK)
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<< HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN);
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hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
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| HINFC504_DMA_PARA_OOB_RW_EN, HINFC504_DMA_PARA);
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} else {
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if (host->command == NAND_CMD_READOOB)
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hinfc_write(host, HINFC504_DMA_PARA_OOB_RW_EN
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| HINFC504_DMA_PARA_OOB_EDC_EN
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| HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
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else
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hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
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| HINFC504_DMA_PARA_OOB_RW_EN
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| HINFC504_DMA_PARA_DATA_EDC_EN
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| HINFC504_DMA_PARA_OOB_EDC_EN
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| HINFC504_DMA_PARA_DATA_ECC_EN
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| HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
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}
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val = (HINFC504_DMA_CTRL_DMA_START | HINFC504_DMA_CTRL_BURST4_EN
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| HINFC504_DMA_CTRL_BURST8_EN | HINFC504_DMA_CTRL_BURST16_EN
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| HINFC504_DMA_CTRL_DATA_AREA_EN | HINFC504_DMA_CTRL_OOB_AREA_EN
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| ((host->addr_cycle == 4 ? 1 : 0)
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<< HINFC504_DMA_CTRL_ADDR_NUM_SHIFT)
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| ((host->chipselect & HINFC504_DMA_CTRL_CS_MASK)
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<< HINFC504_DMA_CTRL_CS_SHIFT));
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if (todev)
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val |= HINFC504_DMA_CTRL_WE;
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init_completion(&host->cmd_complete);
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hinfc_write(host, val, HINFC504_DMA_CTRL);
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ret = wait_for_completion_timeout(&host->cmd_complete,
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HINFC504_NFC_DMA_TIMEOUT);
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if (!ret) {
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dev_err(host->dev, "DMA operation(irq) timeout!\n");
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/* sanity check */
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val = hinfc_read(host, HINFC504_DMA_CTRL);
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if (!(val & HINFC504_DMA_CTRL_DMA_START))
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dev_err(host->dev, "DMA is already done but without irq ACK!\n");
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else
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dev_err(host->dev, "DMA is really timeout!\n");
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}
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}
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static int hisi_nfc_send_cmd_pageprog(struct hinfc_host *host)
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{
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host->addr_value[0] &= 0xffff0000;
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hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
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hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
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hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN,
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HINFC504_CMD);
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hisi_nfc_dma_transfer(host, 1);
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return 0;
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}
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static int hisi_nfc_send_cmd_readstart(struct hinfc_host *host)
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{
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struct mtd_info *mtd = &host->mtd;
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if ((host->addr_value[0] == host->cache_addr_value[0]) &&
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(host->addr_value[1] == host->cache_addr_value[1]))
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return 0;
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host->addr_value[0] &= 0xffff0000;
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hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
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hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
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hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
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HINFC504_CMD);
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hinfc_write(host, 0, HINFC504_LOG_READ_ADDR);
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hinfc_write(host, mtd->writesize + mtd->oobsize,
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HINFC504_LOG_READ_LEN);
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hisi_nfc_dma_transfer(host, 0);
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host->cache_addr_value[0] = host->addr_value[0];
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host->cache_addr_value[1] = host->addr_value[1];
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return 0;
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}
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static int hisi_nfc_send_cmd_erase(struct hinfc_host *host)
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{
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hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
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hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1,
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HINFC504_CMD);
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hinfc_write(host, HINFC504_OP_WAIT_READY_EN
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| HINFC504_OP_CMD2_EN
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| HINFC504_OP_CMD1_EN
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| HINFC504_OP_ADDR_EN
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| ((host->chipselect & HINFC504_OP_NF_CS_MASK)
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<< HINFC504_OP_NF_CS_SHIFT)
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| ((host->addr_cycle & HINFC504_OP_ADDR_CYCLE_MASK)
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<< HINFC504_OP_ADDR_CYCLE_SHIFT),
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HINFC504_OP);
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wait_controller_finished(host);
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return 0;
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}
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static int hisi_nfc_send_cmd_readid(struct hinfc_host *host)
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{
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hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
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hinfc_write(host, NAND_CMD_READID, HINFC504_CMD);
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hinfc_write(host, 0, HINFC504_ADDRL);
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hinfc_write(host, HINFC504_OP_CMD1_EN | HINFC504_OP_ADDR_EN
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| HINFC504_OP_READ_DATA_EN
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| ((host->chipselect & HINFC504_OP_NF_CS_MASK)
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<< HINFC504_OP_NF_CS_SHIFT)
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| 1 << HINFC504_OP_ADDR_CYCLE_SHIFT, HINFC504_OP);
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wait_controller_finished(host);
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return 0;
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}
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static int hisi_nfc_send_cmd_status(struct hinfc_host *host)
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{
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hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
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hinfc_write(host, NAND_CMD_STATUS, HINFC504_CMD);
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hinfc_write(host, HINFC504_OP_CMD1_EN
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| HINFC504_OP_READ_DATA_EN
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| ((host->chipselect & HINFC504_OP_NF_CS_MASK)
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<< HINFC504_OP_NF_CS_SHIFT),
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HINFC504_OP);
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wait_controller_finished(host);
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return 0;
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}
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static int hisi_nfc_send_cmd_reset(struct hinfc_host *host, int chipselect)
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{
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hinfc_write(host, NAND_CMD_RESET, HINFC504_CMD);
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hinfc_write(host, HINFC504_OP_CMD1_EN
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| ((chipselect & HINFC504_OP_NF_CS_MASK)
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<< HINFC504_OP_NF_CS_SHIFT)
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| HINFC504_OP_WAIT_READY_EN,
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HINFC504_OP);
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wait_controller_finished(host);
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return 0;
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}
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static void hisi_nfc_select_chip(struct mtd_info *mtd, int chipselect)
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{
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struct nand_chip *chip = mtd->priv;
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struct hinfc_host *host = chip->priv;
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if (chipselect < 0)
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return;
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host->chipselect = chipselect;
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}
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static uint8_t hisi_nfc_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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struct hinfc_host *host = chip->priv;
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if (host->command == NAND_CMD_STATUS)
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return *(uint8_t *)(host->mmio);
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host->offset++;
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if (host->command == NAND_CMD_READID)
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return *(uint8_t *)(host->mmio + host->offset - 1);
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return *(uint8_t *)(host->buffer + host->offset - 1);
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}
|
|
|
|
static u16 hisi_nfc_read_word(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct hinfc_host *host = chip->priv;
|
|
|
|
host->offset += 2;
|
|
return *(u16 *)(host->buffer + host->offset - 2);
|
|
}
|
|
|
|
static void
|
|
hisi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct hinfc_host *host = chip->priv;
|
|
|
|
memcpy(host->buffer + host->offset, buf, len);
|
|
host->offset += len;
|
|
}
|
|
|
|
static void hisi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct hinfc_host *host = chip->priv;
|
|
|
|
memcpy(buf, host->buffer + host->offset, len);
|
|
host->offset += len;
|
|
}
|
|
|
|
static void set_addr(struct mtd_info *mtd, int column, int page_addr)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct hinfc_host *host = chip->priv;
|
|
unsigned int command = host->command;
|
|
|
|
host->addr_cycle = 0;
|
|
host->addr_value[0] = 0;
|
|
host->addr_value[1] = 0;
|
|
|
|
/* Serially input address */
|
|
if (column != -1) {
|
|
/* Adjust columns for 16 bit buswidth */
|
|
if (chip->options & NAND_BUSWIDTH_16 &&
|
|
!nand_opcode_8bits(command))
|
|
column >>= 1;
|
|
|
|
host->addr_value[0] = column & 0xffff;
|
|
host->addr_cycle = 2;
|
|
}
|
|
if (page_addr != -1) {
|
|
host->addr_value[0] |= (page_addr & 0xffff)
|
|
<< (host->addr_cycle * 8);
|
|
host->addr_cycle += 2;
|
|
/* One more address cycle for devices > 128MiB */
|
|
if (chip->chipsize > (128 << 20)) {
|
|
host->addr_cycle += 1;
|
|
if (host->command == NAND_CMD_ERASE1)
|
|
host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;
|
|
else
|
|
host->addr_value[1] |= ((page_addr >> 16) & 0xff);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void hisi_nfc_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
|
|
int page_addr)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct hinfc_host *host = chip->priv;
|
|
int is_cache_invalid = 1;
|
|
unsigned int flag = 0;
|
|
|
|
host->command = command;
|
|
|
|
switch (command) {
|
|
case NAND_CMD_READ0:
|
|
case NAND_CMD_READOOB:
|
|
if (command == NAND_CMD_READ0)
|
|
host->offset = column;
|
|
else
|
|
host->offset = column + mtd->writesize;
|
|
|
|
is_cache_invalid = 0;
|
|
set_addr(mtd, column, page_addr);
|
|
hisi_nfc_send_cmd_readstart(host);
|
|
break;
|
|
|
|
case NAND_CMD_SEQIN:
|
|
host->offset = column;
|
|
set_addr(mtd, column, page_addr);
|
|
break;
|
|
|
|
case NAND_CMD_ERASE1:
|
|
set_addr(mtd, column, page_addr);
|
|
break;
|
|
|
|
case NAND_CMD_PAGEPROG:
|
|
hisi_nfc_send_cmd_pageprog(host);
|
|
break;
|
|
|
|
case NAND_CMD_ERASE2:
|
|
hisi_nfc_send_cmd_erase(host);
|
|
break;
|
|
|
|
case NAND_CMD_READID:
|
|
host->offset = column;
|
|
memset(host->mmio, 0, 0x10);
|
|
hisi_nfc_send_cmd_readid(host);
|
|
break;
|
|
|
|
case NAND_CMD_STATUS:
|
|
flag = hinfc_read(host, HINFC504_CON);
|
|
if (chip->ecc.mode == NAND_ECC_HW)
|
|
hinfc_write(host,
|
|
flag & ~(HINFC504_CON_ECCTYPE_MASK <<
|
|
HINFC504_CON_ECCTYPE_SHIFT), HINFC504_CON);
|
|
|
|
host->offset = 0;
|
|
memset(host->mmio, 0, 0x10);
|
|
hisi_nfc_send_cmd_status(host);
|
|
hinfc_write(host, flag, HINFC504_CON);
|
|
break;
|
|
|
|
case NAND_CMD_RESET:
|
|
hisi_nfc_send_cmd_reset(host, host->chipselect);
|
|
break;
|
|
|
|
default:
|
|
dev_err(host->dev, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n",
|
|
command, column, page_addr);
|
|
}
|
|
|
|
if (is_cache_invalid) {
|
|
host->cache_addr_value[0] = ~0;
|
|
host->cache_addr_value[1] = ~0;
|
|
}
|
|
}
|
|
|
|
static irqreturn_t hinfc_irq_handle(int irq, void *devid)
|
|
{
|
|
struct hinfc_host *host = devid;
|
|
unsigned int flag;
|
|
|
|
flag = hinfc_read(host, HINFC504_INTS);
|
|
/* store interrupts state */
|
|
host->irq_status |= flag;
|
|
|
|
if (flag & HINFC504_INTS_DMA) {
|
|
hinfc_write(host, HINFC504_INTCLR_DMA, HINFC504_INTCLR);
|
|
complete(&host->cmd_complete);
|
|
} else if (flag & HINFC504_INTS_CE) {
|
|
hinfc_write(host, HINFC504_INTCLR_CE, HINFC504_INTCLR);
|
|
} else if (flag & HINFC504_INTS_UE) {
|
|
hinfc_write(host, HINFC504_INTCLR_UE, HINFC504_INTCLR);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int hisi_nand_read_page_hwecc(struct mtd_info *mtd,
|
|
struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
|
|
{
|
|
struct hinfc_host *host = chip->priv;
|
|
int max_bitflips = 0, stat = 0, stat_max = 0, status_ecc;
|
|
int stat_1, stat_2;
|
|
|
|
chip->read_buf(mtd, buf, mtd->writesize);
|
|
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
/* errors which can not be corrected by ECC */
|
|
if (host->irq_status & HINFC504_INTS_UE) {
|
|
mtd->ecc_stats.failed++;
|
|
} else if (host->irq_status & HINFC504_INTS_CE) {
|
|
/* TODO: need add other ECC modes! */
|
|
switch (chip->ecc.strength) {
|
|
case 16:
|
|
status_ecc = hinfc_read(host, HINFC504_ECC_STATUS) >>
|
|
HINFC504_ECC_16_BIT_SHIFT & 0x0fff;
|
|
stat_2 = status_ecc & 0x3f;
|
|
stat_1 = status_ecc >> 6 & 0x3f;
|
|
stat = stat_1 + stat_2;
|
|
stat_max = max_t(int, stat_1, stat_2);
|
|
}
|
|
mtd->ecc_stats.corrected += stat;
|
|
max_bitflips = max_t(int, max_bitflips, stat_max);
|
|
}
|
|
host->irq_status = 0;
|
|
|
|
return max_bitflips;
|
|
}
|
|
|
|
static int hisi_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
|
|
int page)
|
|
{
|
|
struct hinfc_host *host = chip->priv;
|
|
|
|
chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
|
|
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
if (host->irq_status & HINFC504_INTS_UE) {
|
|
host->irq_status = 0;
|
|
return -EBADMSG;
|
|
}
|
|
|
|
host->irq_status = 0;
|
|
return 0;
|
|
}
|
|
|
|
static int hisi_nand_write_page_hwecc(struct mtd_info *mtd,
|
|
struct nand_chip *chip, const uint8_t *buf, int oob_required)
|
|
{
|
|
chip->write_buf(mtd, buf, mtd->writesize);
|
|
if (oob_required)
|
|
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hisi_nfc_host_init(struct hinfc_host *host)
|
|
{
|
|
struct nand_chip *chip = &host->chip;
|
|
unsigned int flag = 0;
|
|
|
|
host->version = hinfc_read(host, HINFC_VERSION);
|
|
host->addr_cycle = 0;
|
|
host->addr_value[0] = 0;
|
|
host->addr_value[1] = 0;
|
|
host->cache_addr_value[0] = ~0;
|
|
host->cache_addr_value[1] = ~0;
|
|
host->chipselect = 0;
|
|
|
|
/* default page size: 2K, ecc_none. need modify */
|
|
flag = HINFC504_CON_OP_MODE_NORMAL | HINFC504_CON_READY_BUSY_SEL
|
|
| ((0x001 & HINFC504_CON_PAGESIZE_MASK)
|
|
<< HINFC504_CON_PAGEISZE_SHIFT)
|
|
| ((0x0 & HINFC504_CON_ECCTYPE_MASK)
|
|
<< HINFC504_CON_ECCTYPE_SHIFT)
|
|
| ((chip->options & NAND_BUSWIDTH_16) ?
|
|
HINFC504_CON_BUS_WIDTH : 0);
|
|
hinfc_write(host, flag, HINFC504_CON);
|
|
|
|
memset(host->mmio, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN);
|
|
|
|
hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
|
|
HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
|
|
|
|
/* enable DMA irq */
|
|
hinfc_write(host, HINFC504_INTEN_DMA, HINFC504_INTEN);
|
|
}
|
|
|
|
static struct nand_ecclayout nand_ecc_2K_16bits = {
|
|
.oobavail = 6,
|
|
.oobfree = { {2, 6} },
|
|
};
|
|
|
|
static int hisi_nfc_ecc_probe(struct hinfc_host *host)
|
|
{
|
|
unsigned int flag;
|
|
int size, strength, ecc_bits;
|
|
struct device *dev = host->dev;
|
|
struct nand_chip *chip = &host->chip;
|
|
struct mtd_info *mtd = &host->mtd;
|
|
struct device_node *np = host->dev->of_node;
|
|
|
|
size = of_get_nand_ecc_step_size(np);
|
|
strength = of_get_nand_ecc_strength(np);
|
|
if (size != 1024) {
|
|
dev_err(dev, "error ecc size: %d\n", size);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((size == 1024) && ((strength != 8) && (strength != 16) &&
|
|
(strength != 24) && (strength != 40))) {
|
|
dev_err(dev, "ecc size and strength do not match\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip->ecc.size = size;
|
|
chip->ecc.strength = strength;
|
|
|
|
chip->ecc.read_page = hisi_nand_read_page_hwecc;
|
|
chip->ecc.read_oob = hisi_nand_read_oob;
|
|
chip->ecc.write_page = hisi_nand_write_page_hwecc;
|
|
|
|
switch (chip->ecc.strength) {
|
|
case 16:
|
|
ecc_bits = 6;
|
|
if (mtd->writesize == 2048)
|
|
chip->ecc.layout = &nand_ecc_2K_16bits;
|
|
|
|
/* TODO: add more page size support */
|
|
break;
|
|
|
|
/* TODO: add more ecc strength support */
|
|
default:
|
|
dev_err(dev, "not support strength: %d\n", chip->ecc.strength);
|
|
return -EINVAL;
|
|
}
|
|
|
|
flag = hinfc_read(host, HINFC504_CON);
|
|
/* add ecc type configure */
|
|
flag |= ((ecc_bits & HINFC504_CON_ECCTYPE_MASK)
|
|
<< HINFC504_CON_ECCTYPE_SHIFT);
|
|
hinfc_write(host, flag, HINFC504_CON);
|
|
|
|
/* enable ecc irq */
|
|
flag = hinfc_read(host, HINFC504_INTEN) & 0xfff;
|
|
hinfc_write(host, flag | HINFC504_INTEN_UE | HINFC504_INTEN_CE,
|
|
HINFC504_INTEN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int hisi_nfc_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0, irq, buswidth, flag, max_chips = HINFC504_MAX_CHIP;
|
|
struct device *dev = &pdev->dev;
|
|
struct hinfc_host *host;
|
|
struct nand_chip *chip;
|
|
struct mtd_info *mtd;
|
|
struct resource *res;
|
|
struct device_node *np = dev->of_node;
|
|
struct mtd_part_parser_data ppdata;
|
|
|
|
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
|
|
if (!host)
|
|
return -ENOMEM;
|
|
host->dev = dev;
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
chip = &host->chip;
|
|
mtd = &host->mtd;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(dev, "no IRQ resource defined\n");
|
|
ret = -ENXIO;
|
|
goto err_res;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
host->iobase = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(host->iobase)) {
|
|
ret = PTR_ERR(host->iobase);
|
|
goto err_res;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
host->mmio = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(host->mmio)) {
|
|
ret = PTR_ERR(host->mmio);
|
|
dev_err(dev, "devm_ioremap_resource[1] fail\n");
|
|
goto err_res;
|
|
}
|
|
|
|
mtd->priv = chip;
|
|
mtd->owner = THIS_MODULE;
|
|
mtd->name = "hisi_nand";
|
|
mtd->dev.parent = &pdev->dev;
|
|
|
|
chip->priv = host;
|
|
chip->cmdfunc = hisi_nfc_cmdfunc;
|
|
chip->select_chip = hisi_nfc_select_chip;
|
|
chip->read_byte = hisi_nfc_read_byte;
|
|
chip->read_word = hisi_nfc_read_word;
|
|
chip->write_buf = hisi_nfc_write_buf;
|
|
chip->read_buf = hisi_nfc_read_buf;
|
|
chip->chip_delay = HINFC504_CHIP_DELAY;
|
|
|
|
chip->ecc.mode = of_get_nand_ecc_mode(np);
|
|
|
|
buswidth = of_get_nand_bus_width(np);
|
|
if (buswidth == 16)
|
|
chip->options |= NAND_BUSWIDTH_16;
|
|
|
|
hisi_nfc_host_init(host);
|
|
|
|
ret = devm_request_irq(dev, irq, hinfc_irq_handle, 0x0, "nandc", host);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request IRQ\n");
|
|
goto err_res;
|
|
}
|
|
|
|
ret = nand_scan_ident(mtd, max_chips, NULL);
|
|
if (ret) {
|
|
ret = -ENODEV;
|
|
goto err_res;
|
|
}
|
|
|
|
host->buffer = dmam_alloc_coherent(dev, mtd->writesize + mtd->oobsize,
|
|
&host->dma_buffer, GFP_KERNEL);
|
|
if (!host->buffer) {
|
|
ret = -ENOMEM;
|
|
goto err_res;
|
|
}
|
|
|
|
host->dma_oob = host->dma_buffer + mtd->writesize;
|
|
memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
|
|
|
|
flag = hinfc_read(host, HINFC504_CON);
|
|
flag &= ~(HINFC504_CON_PAGESIZE_MASK << HINFC504_CON_PAGEISZE_SHIFT);
|
|
switch (mtd->writesize) {
|
|
case 2048:
|
|
flag |= (0x001 << HINFC504_CON_PAGEISZE_SHIFT); break;
|
|
/*
|
|
* TODO: add more pagesize support,
|
|
* default pagesize has been set in hisi_nfc_host_init
|
|
*/
|
|
default:
|
|
dev_err(dev, "NON-2KB page size nand flash\n");
|
|
ret = -EINVAL;
|
|
goto err_res;
|
|
}
|
|
hinfc_write(host, flag, HINFC504_CON);
|
|
|
|
if (chip->ecc.mode == NAND_ECC_HW)
|
|
hisi_nfc_ecc_probe(host);
|
|
|
|
ret = nand_scan_tail(mtd);
|
|
if (ret) {
|
|
dev_err(dev, "nand_scan_tail failed: %d\n", ret);
|
|
goto err_res;
|
|
}
|
|
|
|
ppdata.of_node = np;
|
|
ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
|
|
if (ret) {
|
|
dev_err(dev, "Err MTD partition=%d\n", ret);
|
|
goto err_mtd;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_mtd:
|
|
nand_release(mtd);
|
|
err_res:
|
|
return ret;
|
|
}
|
|
|
|
static int hisi_nfc_remove(struct platform_device *pdev)
|
|
{
|
|
struct hinfc_host *host = platform_get_drvdata(pdev);
|
|
struct mtd_info *mtd = &host->mtd;
|
|
|
|
nand_release(mtd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int hisi_nfc_suspend(struct device *dev)
|
|
{
|
|
struct hinfc_host *host = dev_get_drvdata(dev);
|
|
unsigned long timeout = jiffies + HINFC504_NFC_PM_TIMEOUT;
|
|
|
|
while (time_before(jiffies, timeout)) {
|
|
if (((hinfc_read(host, HINFC504_STATUS) & 0x1) == 0x0) &&
|
|
(hinfc_read(host, HINFC504_DMA_CTRL) &
|
|
HINFC504_DMA_CTRL_DMA_START)) {
|
|
cond_resched();
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
dev_err(host->dev, "nand controller suspend timeout.\n");
|
|
|
|
return -EAGAIN;
|
|
}
|
|
|
|
static int hisi_nfc_resume(struct device *dev)
|
|
{
|
|
int cs;
|
|
struct hinfc_host *host = dev_get_drvdata(dev);
|
|
struct nand_chip *chip = &host->chip;
|
|
|
|
for (cs = 0; cs < chip->numchips; cs++)
|
|
hisi_nfc_send_cmd_reset(host, cs);
|
|
hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
|
|
HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops, hisi_nfc_suspend, hisi_nfc_resume);
|
|
|
|
static const struct of_device_id nfc_id_table[] = {
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{ .compatible = "hisilicon,504-nfc" },
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{}
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};
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MODULE_DEVICE_TABLE(of, nfc_id_table);
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|
|
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static struct platform_driver hisi_nfc_driver = {
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.driver = {
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.name = "hisi_nand",
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.of_match_table = nfc_id_table,
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.pm = &hisi_nfc_pm_ops,
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|
},
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.probe = hisi_nfc_probe,
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.remove = hisi_nfc_remove,
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};
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|
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module_platform_driver(hisi_nfc_driver);
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|
|
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Zhou Wang");
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|
MODULE_AUTHOR("Zhiyong Cai");
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MODULE_DESCRIPTION("Hisilicon Nand Flash Controller Driver");
|