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![Lars-Peter Clausen](/assets/img/avatar_default.png)
Use the GPIO descriptor API instead of the deprecated legacy GPIO API to manage the busy GPIO. The patch updates both the jz4740 nand driver and the only user of the driver the qi-lb60 board driver. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
579 lines
15 KiB
C
579 lines
15 KiB
C
/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 SoC NAND controller driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/gpio.h>
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#include <asm/mach-jz4740/jz4740_nand.h>
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#define JZ_REG_NAND_CTRL 0x50
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#define JZ_REG_NAND_ECC_CTRL 0x100
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#define JZ_REG_NAND_DATA 0x104
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#define JZ_REG_NAND_PAR0 0x108
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#define JZ_REG_NAND_PAR1 0x10C
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#define JZ_REG_NAND_PAR2 0x110
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#define JZ_REG_NAND_IRQ_STAT 0x114
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#define JZ_REG_NAND_IRQ_CTRL 0x118
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#define JZ_REG_NAND_ERR(x) (0x11C + ((x) << 2))
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#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
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#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
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#define JZ_NAND_ECC_CTRL_RS BIT(2)
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#define JZ_NAND_ECC_CTRL_RESET BIT(1)
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#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
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#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
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#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
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#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
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#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
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#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
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#define JZ_NAND_STATUS_ERROR BIT(0)
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#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
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#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
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#define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
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#define JZ_NAND_MEM_CMD_OFFSET 0x08000
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#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
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struct jz_nand {
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struct mtd_info mtd;
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struct nand_chip chip;
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void __iomem *base;
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struct resource *mem;
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unsigned char banks[JZ_NAND_NUM_BANKS];
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void __iomem *bank_base[JZ_NAND_NUM_BANKS];
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struct resource *bank_mem[JZ_NAND_NUM_BANKS];
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int selected_bank;
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struct gpio_desc *busy_gpio;
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bool is_reading;
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};
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static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
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{
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return container_of(mtd, struct jz_nand, mtd);
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}
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static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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struct nand_chip *chip = mtd->priv;
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uint32_t ctrl;
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int banknr;
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ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
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ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
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if (chipnr == -1) {
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banknr = -1;
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} else {
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banknr = nand->banks[chipnr] - 1;
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chip->IO_ADDR_R = nand->bank_base[banknr];
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chip->IO_ADDR_W = nand->bank_base[banknr];
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}
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writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
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nand->selected_bank = banknr;
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}
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static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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struct nand_chip *chip = mtd->priv;
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uint32_t reg;
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void __iomem *bank_base = nand->bank_base[nand->selected_bank];
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BUG_ON(nand->selected_bank < 0);
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if (ctrl & NAND_CTRL_CHANGE) {
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BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
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if (ctrl & NAND_ALE)
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bank_base += JZ_NAND_MEM_ADDR_OFFSET;
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else if (ctrl & NAND_CLE)
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bank_base += JZ_NAND_MEM_CMD_OFFSET;
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chip->IO_ADDR_W = bank_base;
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reg = readl(nand->base + JZ_REG_NAND_CTRL);
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if (ctrl & NAND_NCE)
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reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
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else
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reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
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writel(reg, nand->base + JZ_REG_NAND_CTRL);
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}
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if (dat != NAND_CMD_NONE)
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writeb(dat, chip->IO_ADDR_W);
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}
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static int jz_nand_dev_ready(struct mtd_info *mtd)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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return gpiod_get_value_cansleep(nand->busy_gpio);
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}
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static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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uint32_t reg;
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writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg |= JZ_NAND_ECC_CTRL_RESET;
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reg |= JZ_NAND_ECC_CTRL_ENABLE;
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reg |= JZ_NAND_ECC_CTRL_RS;
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switch (mode) {
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case NAND_ECC_READ:
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reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
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nand->is_reading = true;
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break;
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case NAND_ECC_WRITE:
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reg |= JZ_NAND_ECC_CTRL_ENCODING;
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nand->is_reading = false;
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break;
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default:
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break;
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}
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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}
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static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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uint32_t reg, status;
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int i;
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unsigned int timeout = 1000;
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static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
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0x8b, 0xff, 0xb7, 0x6f};
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if (nand->is_reading)
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return 0;
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do {
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status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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} while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
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if (timeout == 0)
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return -1;
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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for (i = 0; i < 9; ++i)
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ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
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/* If the written data is completly 0xff, we also want to write 0xff as
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* ecc, otherwise we will get in trouble when doing subpage writes. */
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if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
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memset(ecc_code, 0xff, 9);
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return 0;
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}
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static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
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{
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int offset = index & 0x7;
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uint16_t data;
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index += (index >> 3);
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data = dat[index];
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data |= dat[index+1] << 8;
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mask ^= (data >> offset) & 0x1ff;
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data &= ~(0x1ff << offset);
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data |= (mask << offset);
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dat[index] = data & 0xff;
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dat[index+1] = (data >> 8) & 0xff;
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}
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static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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int i, error_count, index;
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uint32_t reg, status, error;
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uint32_t t;
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unsigned int timeout = 1000;
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t = read_ecc[0];
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if (t == 0xff) {
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for (i = 1; i < 9; ++i)
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t &= read_ecc[i];
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t &= dat[0];
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t &= dat[nand->chip.ecc.size / 2];
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t &= dat[nand->chip.ecc.size - 1];
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if (t == 0xff) {
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for (i = 1; i < nand->chip.ecc.size - 1; ++i)
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t &= dat[i];
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if (t == 0xff)
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return 0;
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}
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}
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for (i = 0; i < 9; ++i)
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writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg |= JZ_NAND_ECC_CTRL_PAR_READY;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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do {
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status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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} while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
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if (timeout == 0)
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return -1;
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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if (status & JZ_NAND_STATUS_ERROR) {
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if (status & JZ_NAND_STATUS_UNCOR_ERROR)
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return -1;
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error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
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for (i = 0; i < error_count; ++i) {
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error = readl(nand->base + JZ_REG_NAND_ERR(i));
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index = ((error >> 16) & 0x1ff) - 1;
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if (index >= 0 && index < 512)
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jz_nand_correct_data(dat, index, error & 0x1ff);
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}
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return error_count;
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}
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return 0;
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}
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static int jz_nand_ioremap_resource(struct platform_device *pdev,
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const char *name, struct resource **res, void *__iomem *base)
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{
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int ret;
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*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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if (!*res) {
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dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
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ret = -ENXIO;
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goto err;
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}
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*res = request_mem_region((*res)->start, resource_size(*res),
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pdev->name);
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if (!*res) {
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dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
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ret = -EBUSY;
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goto err;
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}
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*base = ioremap((*res)->start, resource_size(*res));
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if (!*base) {
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dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
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ret = -EBUSY;
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goto err_release_mem;
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}
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return 0;
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err_release_mem:
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release_mem_region((*res)->start, resource_size(*res));
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err:
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*res = NULL;
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*base = NULL;
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return ret;
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}
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static inline void jz_nand_iounmap_resource(struct resource *res,
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void __iomem *base)
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{
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iounmap(base);
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release_mem_region(res->start, resource_size(res));
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}
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static int jz_nand_detect_bank(struct platform_device *pdev,
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struct jz_nand *nand, unsigned char bank,
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size_t chipnr, uint8_t *nand_maf_id,
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uint8_t *nand_dev_id)
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{
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int ret;
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int gpio;
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char gpio_name[9];
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char res_name[6];
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uint32_t ctrl;
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struct mtd_info *mtd = &nand->mtd;
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struct nand_chip *chip = &nand->chip;
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/* Request GPIO port. */
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gpio = JZ_GPIO_MEM_CS0 + bank - 1;
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sprintf(gpio_name, "NAND CS%d", bank);
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ret = gpio_request(gpio, gpio_name);
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if (ret) {
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dev_warn(&pdev->dev,
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"Failed to request %s gpio %d: %d\n",
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gpio_name, gpio, ret);
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goto notfound_gpio;
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}
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/* Request I/O resource. */
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sprintf(res_name, "bank%d", bank);
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ret = jz_nand_ioremap_resource(pdev, res_name,
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&nand->bank_mem[bank - 1],
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&nand->bank_base[bank - 1]);
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if (ret)
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goto notfound_resource;
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/* Enable chip in bank. */
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jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
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ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
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ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
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writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
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if (chipnr == 0) {
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/* Detect first chip. */
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ret = nand_scan_ident(mtd, 1, NULL);
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if (ret)
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goto notfound_id;
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/* Retrieve the IDs from the first chip. */
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chip->select_chip(mtd, 0);
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chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
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chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
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*nand_maf_id = chip->read_byte(mtd);
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*nand_dev_id = chip->read_byte(mtd);
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} else {
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/* Detect additional chip. */
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chip->select_chip(mtd, chipnr);
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chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
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chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
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if (*nand_maf_id != chip->read_byte(mtd)
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|| *nand_dev_id != chip->read_byte(mtd)) {
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ret = -ENODEV;
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goto notfound_id;
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}
|
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|
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/* Update size of the MTD. */
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chip->numchips++;
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mtd->size += chip->chipsize;
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}
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dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank);
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return 0;
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notfound_id:
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dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
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ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
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writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
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jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
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jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
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nand->bank_base[bank - 1]);
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notfound_resource:
|
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gpio_free(gpio);
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notfound_gpio:
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return ret;
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}
|
|
|
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static int jz_nand_probe(struct platform_device *pdev)
|
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{
|
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int ret;
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struct jz_nand *nand;
|
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struct nand_chip *chip;
|
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struct mtd_info *mtd;
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struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
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size_t chipnr, bank_idx;
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uint8_t nand_maf_id = 0, nand_dev_id = 0;
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|
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nand = kzalloc(sizeof(*nand), GFP_KERNEL);
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if (!nand)
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return -ENOMEM;
|
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|
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ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
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if (ret)
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goto err_free;
|
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|
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nand->busy_gpio = devm_gpiod_get_optional(&pdev->dev, "busy", GPIOD_IN);
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if (IS_ERR(nand->busy_gpio)) {
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ret = PTR_ERR(nand->busy_gpio);
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dev_err(&pdev->dev, "Failed to request busy gpio %d\n",
|
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ret);
|
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goto err_iounmap_mmio;
|
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}
|
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|
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mtd = &nand->mtd;
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chip = &nand->chip;
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mtd->priv = chip;
|
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mtd->owner = THIS_MODULE;
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mtd->name = "jz4740-nand";
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|
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chip->ecc.hwctl = jz_nand_hwctl;
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chip->ecc.calculate = jz_nand_calculate_ecc_rs;
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chip->ecc.correct = jz_nand_correct_ecc_rs;
|
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chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
|
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chip->ecc.size = 512;
|
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chip->ecc.bytes = 9;
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chip->ecc.strength = 4;
|
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|
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if (pdata)
|
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chip->ecc.layout = pdata->ecc_layout;
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|
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chip->chip_delay = 50;
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chip->cmd_ctrl = jz_nand_cmd_ctrl;
|
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chip->select_chip = jz_nand_select_chip;
|
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|
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if (nand->busy_gpio)
|
|
chip->dev_ready = jz_nand_dev_ready;
|
|
|
|
platform_set_drvdata(pdev, nand);
|
|
|
|
/* We are going to autodetect NAND chips in the banks specified in the
|
|
* platform data. Although nand_scan_ident() can detect multiple chips,
|
|
* it requires those chips to be numbered consecuitively, which is not
|
|
* always the case for external memory banks. And a fixed chip-to-bank
|
|
* mapping is not practical either, since for example Dingoo units
|
|
* produced at different times have NAND chips in different banks.
|
|
*/
|
|
chipnr = 0;
|
|
for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
|
|
unsigned char bank;
|
|
|
|
/* If there is no platform data, look for NAND in bank 1,
|
|
* which is the most likely bank since it is the only one
|
|
* that can be booted from.
|
|
*/
|
|
bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
|
|
if (bank == 0)
|
|
break;
|
|
if (bank > JZ_NAND_NUM_BANKS) {
|
|
dev_warn(&pdev->dev,
|
|
"Skipping non-existing bank: %d\n", bank);
|
|
continue;
|
|
}
|
|
/* The detection routine will directly or indirectly call
|
|
* jz_nand_select_chip(), so nand->banks has to contain the
|
|
* bank we're checking.
|
|
*/
|
|
nand->banks[chipnr] = bank;
|
|
if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
|
|
&nand_maf_id, &nand_dev_id) == 0)
|
|
chipnr++;
|
|
else
|
|
nand->banks[chipnr] = 0;
|
|
}
|
|
if (chipnr == 0) {
|
|
dev_err(&pdev->dev, "No NAND chips found\n");
|
|
goto err_iounmap_mmio;
|
|
}
|
|
|
|
if (pdata && pdata->ident_callback) {
|
|
pdata->ident_callback(pdev, chip, &pdata->partitions,
|
|
&pdata->num_partitions);
|
|
}
|
|
|
|
ret = nand_scan_tail(mtd);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to scan NAND\n");
|
|
goto err_unclaim_banks;
|
|
}
|
|
|
|
ret = mtd_device_parse_register(mtd, NULL, NULL,
|
|
pdata ? pdata->partitions : NULL,
|
|
pdata ? pdata->num_partitions : 0);
|
|
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to add mtd device\n");
|
|
goto err_nand_release;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
|
|
|
|
return 0;
|
|
|
|
err_nand_release:
|
|
nand_release(mtd);
|
|
err_unclaim_banks:
|
|
while (chipnr--) {
|
|
unsigned char bank = nand->banks[chipnr];
|
|
gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
|
|
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
|
|
nand->bank_base[bank - 1]);
|
|
}
|
|
writel(0, nand->base + JZ_REG_NAND_CTRL);
|
|
err_iounmap_mmio:
|
|
jz_nand_iounmap_resource(nand->mem, nand->base);
|
|
err_free:
|
|
kfree(nand);
|
|
return ret;
|
|
}
|
|
|
|
static int jz_nand_remove(struct platform_device *pdev)
|
|
{
|
|
struct jz_nand *nand = platform_get_drvdata(pdev);
|
|
size_t i;
|
|
|
|
nand_release(&nand->mtd);
|
|
|
|
/* Deassert and disable all chips */
|
|
writel(0, nand->base + JZ_REG_NAND_CTRL);
|
|
|
|
for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
|
|
unsigned char bank = nand->banks[i];
|
|
if (bank != 0) {
|
|
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
|
|
nand->bank_base[bank - 1]);
|
|
gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
|
|
}
|
|
}
|
|
|
|
jz_nand_iounmap_resource(nand->mem, nand->base);
|
|
|
|
kfree(nand);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver jz_nand_driver = {
|
|
.probe = jz_nand_probe,
|
|
.remove = jz_nand_remove,
|
|
.driver = {
|
|
.name = "jz4740-nand",
|
|
},
|
|
};
|
|
|
|
module_platform_driver(jz_nand_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
|
|
MODULE_ALIAS("platform:jz4740-nand");
|