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88807dc8d5
Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will expose more than
desired registers to process space.
v2: Use explicit register hole location
v3: Moved remapped hdp registers into adev struct
v4: Use more generic name for remapped page
Expose register offset in kfd_ioctl.h
v5: Move hdp register remap function to nbio ip function
v6: Fixed operator precedence issue and other bugs
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
274 lines
9.5 KiB
C
274 lines
9.5 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "nbio_v7_4.h"
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#include "nbio/nbio_7_4_offset.h"
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#include "nbio/nbio_7_4_sh_mask.h"
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#include "nbio/nbio_7_4_0_smn.h"
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#include <uapi/linux/kfd_ioctl.h>
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#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
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static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
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{
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WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
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WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
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}
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static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
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{
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u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
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tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
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return tmp;
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}
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static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
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BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
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}
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static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg)
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WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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else
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amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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}
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static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
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{
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return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
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}
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static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
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bool use_doorbell, int doorbell_index, int doorbell_size)
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{
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u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
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SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
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u32 doorbell_range = RREG32(reg);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
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} else
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doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
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WREG32(reg, doorbell_range);
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}
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static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
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}
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static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp = 0;
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if (enable) {
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tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
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REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
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REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
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WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
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lower_32_bits(adev->doorbell.base));
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WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
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upper_32_bits(adev->doorbell.base));
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}
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WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
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}
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static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index)
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{
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u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
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if (use_doorbell) {
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
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} else
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
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WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
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}
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static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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//TODO: Add support for v7.4
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}
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static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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def = data = RREG32_PCIE(smnPCIE_CNTL2);
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
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data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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} else {
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data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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}
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if (def != data)
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WREG32_PCIE(smnPCIE_CNTL2, data);
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}
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static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
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u32 *flags)
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{
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int data;
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/* AMD_CG_SUPPORT_BIF_MGCG */
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data = RREG32_PCIE(smnCPM_CONTROL);
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if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_MGCG;
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/* AMD_CG_SUPPORT_BIF_LS */
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data = RREG32_PCIE(smnPCIE_CNTL2);
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if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_LS;
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}
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static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
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{
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u32 interrupt_cntl;
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/* setup interrupt control */
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WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
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interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
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/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
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* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
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*/
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
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/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
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WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
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}
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static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
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}
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static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
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}
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static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
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}
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static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
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}
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static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
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.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
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.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
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.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
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.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
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.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
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.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
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.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
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.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
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.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
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.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
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.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
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.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
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};
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static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
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{
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uint32_t reg;
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reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);
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if (reg & 1)
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
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if (reg & 0x80000000)
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
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if (!reg) {
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if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
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adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
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}
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}
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static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
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{
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uint32_t def, data;
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def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
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data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
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if (def != data)
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WREG32_PCIE(smnPCIE_CI_CNTL, data);
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}
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const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
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.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
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.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
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.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
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.get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
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.get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
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.get_rev_id = nbio_v7_4_get_rev_id,
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.mc_access_enable = nbio_v7_4_mc_access_enable,
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.hdp_flush = nbio_v7_4_hdp_flush,
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.get_memsize = nbio_v7_4_get_memsize,
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.sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
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.enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
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.enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
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.ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
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.update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
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.update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
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.get_clockgating_state = nbio_v7_4_get_clockgating_state,
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.ih_control = nbio_v7_4_ih_control,
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.init_registers = nbio_v7_4_init_registers,
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.detect_hw_virt = nbio_v7_4_detect_hw_virt,
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.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
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};
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