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87e2fc3750
The Marvell Armada 38x SoCs contains two xHCI controllers. This commit adds the Device Tree description of those interfaces at the SoC level, and also enables the two USB3 ports on the Armada 385 DB platform and one USB3 port on the Armada 385 RD platform. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1400149062-32661-15-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
97 lines
1.8 KiB
Text
97 lines
1.8 KiB
Text
/*
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* Device Tree file for Marvell Armada 385 Reference Design board
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* (RD-88F6820-AP)
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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#include "armada-385.dtsi"
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/ {
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model = "Marvell Armada 385 Reference Design";
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compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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internal-regs {
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spi@10600 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p128";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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i2c@11000 {
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status = "okay";
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clock-frequency = <100000>;
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};
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serial@12000 {
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status = "okay";
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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usb3@f0000 {
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status = "okay";
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* One PCIe units is accessible through
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* standard PCIe slot on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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