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c52d0d30ae
This is a preliminary patch to add a vdso to all user processes. Still missing are ELF headers and .eh_frame information. But it is enough to allow us to move signal trampolines off of the stack. Note that emulation of branch delay slots in the FPU emulator still requires the stack. We allocate a single page (the vdso) and write all possible signal trampolines into it. The stack is moved down by one page and the vdso is mapped into this space. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/975/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
328 lines
8.9 KiB
C
328 lines
8.9 KiB
C
/*
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* Switch a MMU context.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_MMU_CONTEXT_H
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#define _ASM_MMU_CONTEXT_H
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/slab.h>
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#include <asm/cacheflush.h>
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#include <asm/hazards.h>
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#include <asm/tlbflush.h>
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/mipsmtregs.h>
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#include <asm/smtc.h>
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#endif /* SMTC */
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#include <asm-generic/mm_hooks.h>
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#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
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#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
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tlbmiss_handler_setup_pgd((unsigned long)(pgd))
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static inline void tlbmiss_handler_setup_pgd(unsigned long pgd)
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{
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/* Check for swapper_pg_dir and convert to physical address. */
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if ((pgd & CKSEG3) == CKSEG0)
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pgd = CPHYSADDR(pgd);
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write_c0_context(pgd << 11);
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}
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#define TLBMISS_HANDLER_SETUP() \
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do { \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
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write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
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} while (0)
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static inline unsigned long get_current_pgd(void)
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{
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return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
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}
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#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
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/*
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* For the fast tlb miss handlers, we keep a per cpu array of pointers
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* to the current pgd for each processor. Also, the proc. id is stuffed
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* into the context register.
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*/
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extern unsigned long pgd_current[];
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#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
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pgd_current[smp_processor_id()] = (unsigned long)(pgd)
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#ifdef CONFIG_32BIT
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#define TLBMISS_HANDLER_SETUP() \
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write_c0_context((unsigned long) smp_processor_id() << 25); \
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back_to_back_c0_hazard(); \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
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#endif
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#ifdef CONFIG_64BIT
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#define TLBMISS_HANDLER_SETUP() \
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write_c0_context((unsigned long) smp_processor_id() << 26); \
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back_to_back_c0_hazard(); \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
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#endif
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define ASID_INC 0x40
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#define ASID_MASK 0xfc0
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#elif defined(CONFIG_CPU_R8000)
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#define ASID_INC 0x10
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#define ASID_MASK 0xff0
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#elif defined(CONFIG_CPU_RM9000)
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#define ASID_INC 0x1
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#define ASID_MASK 0xfff
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/* SMTC/34K debug hack - but maybe we'll keep it */
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#elif defined(CONFIG_MIPS_MT_SMTC)
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#define ASID_INC 0x1
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extern unsigned long smtc_asid_mask;
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#define ASID_MASK (smtc_asid_mask)
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#define HW_ASID_MASK 0xff
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/* End SMTC/34K debug hack */
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#else /* FIXME: not correct for R6000 */
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#define ASID_INC 0x1
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#define ASID_MASK 0xff
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#endif
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#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
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#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
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#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/*
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* All unused by hardware upper bits will be considered
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* as a software asid extension.
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*/
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#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
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#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
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#ifndef CONFIG_MIPS_MT_SMTC
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/* Normal, classic MIPS get_new_mmu_context */
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static inline void
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get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
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{
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unsigned long asid = asid_cache(cpu);
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if (! ((asid += ASID_INC) & ASID_MASK) ) {
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if (cpu_has_vtag_icache)
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flush_icache_all();
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local_flush_tlb_all(); /* start new asid cycle */
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if (!asid) /* fix version if needed */
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asid = ASID_FIRST_VERSION;
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}
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cpu_context(cpu, mm) = asid_cache(cpu) = asid;
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}
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#else /* CONFIG_MIPS_MT_SMTC */
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#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
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#endif /* CONFIG_MIPS_MT_SMTC */
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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static inline int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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int i;
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for_each_online_cpu(i)
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cpu_context(i, mm) = 0;
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return 0;
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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unsigned long flags;
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#ifdef CONFIG_MIPS_MT_SMTC
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unsigned long oldasid;
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unsigned long mtflags;
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int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
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local_irq_save(flags);
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mtflags = dvpe();
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#else /* Not SMTC */
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local_irq_save(flags);
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#endif /* CONFIG_MIPS_MT_SMTC */
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/* Check if our ASID is of an older version and thus invalid */
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if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
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get_new_mmu_context(next, cpu);
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* If the EntryHi ASID being replaced happens to be
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* the value flagged at ASID recycling time as having
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* an extended life, clear the bit showing it being
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* in use by this "CPU", and if that's the last bit,
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* free up the ASID value for use and flush any old
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* instances of it from the TLB.
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*/
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oldasid = (read_c0_entryhi() & ASID_MASK);
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if(smtc_live_asid[mytlb][oldasid]) {
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smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
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if(smtc_live_asid[mytlb][oldasid] == 0)
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smtc_flush_tlb_asid(oldasid);
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}
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/*
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* Tread softly on EntryHi, and so long as we support
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* having ASID_MASK smaller than the hardware maximum,
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* make sure no "soft" bits become "hard"...
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*/
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write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
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cpu_asid(cpu, next));
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ehb(); /* Make sure it propagates to TCStatus */
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evpe(mtflags);
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#else
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write_c0_entryhi(cpu_asid(cpu, next));
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#endif /* CONFIG_MIPS_MT_SMTC */
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TLBMISS_HANDLER_SETUP_PGD(next->pgd);
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/*
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* Mark current->active_mm as not "active" anymore.
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* We don't want to mislead possible IPI tlb flush routines.
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*/
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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local_irq_restore(flags);
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}
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/*
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* Destroy context related info for an mm_struct that is about
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* to be put to rest.
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*/
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static inline void destroy_context(struct mm_struct *mm)
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{
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}
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#define deactivate_mm(tsk, mm) do { } while (0)
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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static inline void
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activate_mm(struct mm_struct *prev, struct mm_struct *next)
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{
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unsigned long flags;
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unsigned int cpu = smp_processor_id();
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#ifdef CONFIG_MIPS_MT_SMTC
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unsigned long oldasid;
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unsigned long mtflags;
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int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
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#endif /* CONFIG_MIPS_MT_SMTC */
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local_irq_save(flags);
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/* Unconditionally get a new ASID. */
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get_new_mmu_context(next, cpu);
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#ifdef CONFIG_MIPS_MT_SMTC
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/* See comments for similar code above */
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mtflags = dvpe();
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oldasid = read_c0_entryhi() & ASID_MASK;
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if(smtc_live_asid[mytlb][oldasid]) {
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smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
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if(smtc_live_asid[mytlb][oldasid] == 0)
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smtc_flush_tlb_asid(oldasid);
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}
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/* See comments for similar code above */
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write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
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cpu_asid(cpu, next));
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ehb(); /* Make sure it propagates to TCStatus */
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evpe(mtflags);
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#else
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write_c0_entryhi(cpu_asid(cpu, next));
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#endif /* CONFIG_MIPS_MT_SMTC */
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TLBMISS_HANDLER_SETUP_PGD(next->pgd);
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/* mark mmu ownership change */
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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local_irq_restore(flags);
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}
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/*
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* If mm is currently active_mm, we can't really drop it. Instead,
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* we will get a new one for it.
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*/
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static inline void
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drop_mmu_context(struct mm_struct *mm, unsigned cpu)
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{
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unsigned long flags;
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#ifdef CONFIG_MIPS_MT_SMTC
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unsigned long oldasid;
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/* Can't use spinlock because called from TLB flush within DVPE */
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unsigned int prevvpe;
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int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
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#endif /* CONFIG_MIPS_MT_SMTC */
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local_irq_save(flags);
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if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
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get_new_mmu_context(mm, cpu);
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#ifdef CONFIG_MIPS_MT_SMTC
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/* See comments for similar code above */
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prevvpe = dvpe();
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oldasid = (read_c0_entryhi() & ASID_MASK);
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if (smtc_live_asid[mytlb][oldasid]) {
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smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
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if(smtc_live_asid[mytlb][oldasid] == 0)
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smtc_flush_tlb_asid(oldasid);
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}
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/* See comments for similar code above */
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write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
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| cpu_asid(cpu, mm));
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ehb(); /* Make sure it propagates to TCStatus */
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evpe(prevvpe);
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#else /* not CONFIG_MIPS_MT_SMTC */
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write_c0_entryhi(cpu_asid(cpu, mm));
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#endif /* CONFIG_MIPS_MT_SMTC */
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} else {
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/* will get a new context next time */
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#ifndef CONFIG_MIPS_MT_SMTC
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cpu_context(cpu, mm) = 0;
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#else /* SMTC */
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int i;
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/* SMTC shares the TLB (and ASIDs) across VPEs */
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for_each_online_cpu(i) {
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if((smtc_status & SMTC_TLB_SHARED)
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|| (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
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cpu_context(i, mm) = 0;
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}
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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local_irq_restore(flags);
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}
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#endif /* _ASM_MMU_CONTEXT_H */
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