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![Kevin D. Kissell](/assets/img/avatar_default.png)
1. At the end of smtc_distribute_timer, nextstamp is valid and has already passed so we goto repeat. 2. Nothing updates nextstamp (only updated if the timeout is in the future And we just decided it is in the past) 3. At the end nextstamp still has the same value so it is still valid and in the past. 4. This repeats until read_c0_count has a value which causes nextstamp to be in the future. Reported and initial patch and testing by Mikael Starvik <mikael.starvik@axis.com>. Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Cc: Mikael Starvik <mikael.starvik@axis.com> Cc: linux-mips@linux-mips.org Cc: Jesper Nilsson <Jesper.Nilsson@axis.com> Patchwork: http://patchwork.linux-mips.org/patch/621/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
323 lines
8.7 KiB
C
323 lines
8.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 MIPS Technologies, Inc.
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* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
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* Copyright (C) 2008 Kevin D. Kissell, Paralogos sarl
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/smp.h>
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#include <asm/smtc_ipi.h>
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#include <asm/time.h>
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#include <asm/cevt-r4k.h>
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/*
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* Variant clock event timer support for SMTC on MIPS 34K, 1004K
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* or other MIPS MT cores.
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*
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* Notes on SMTC Support:
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*
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* SMTC has multiple microthread TCs pretending to be Linux CPUs.
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* But there's only one Count/Compare pair per VPE, and Compare
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* interrupts are taken opportunisitically by available TCs
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* bound to the VPE with the Count register. The new timer
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* framework provides for global broadcasts, but we really
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* want VPE-level multicasts for best behavior. So instead
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* of invoking the high-level clock-event broadcast code,
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* this version of SMTC support uses the historical SMTC
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* multicast mechanisms "under the hood", appearing to the
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* generic clock layer as if the interrupts are per-CPU.
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*
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* The approach taken here is to maintain a set of NR_CPUS
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* virtual timers, and track which "CPU" needs to be alerted
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* at each event.
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*
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* It's unlikely that we'll see a MIPS MT core with more than
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* 2 VPEs, but we *know* that we won't need to handle more
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* VPEs than we have "CPUs". So NCPUs arrays of NCPUs elements
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* is always going to be overkill, but always going to be enough.
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*/
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unsigned long smtc_nexttime[NR_CPUS][NR_CPUS];
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static int smtc_nextinvpe[NR_CPUS];
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/*
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* Timestamps stored are absolute values to be programmed
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* into Count register. Valid timestamps will never be zero.
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* If a Zero Count value is actually calculated, it is converted
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* to be a 1, which will introduce 1 or two CPU cycles of error
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* roughly once every four billion events, which at 1000 HZ means
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* about once every 50 days. If that's actually a problem, one
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* could alternate squashing 0 to 1 and to -1.
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*/
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#define MAKEVALID(x) (((x) == 0L) ? 1L : (x))
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#define ISVALID(x) ((x) != 0L)
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/*
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* Time comparison is subtle, as it's really truncated
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* modular arithmetic.
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*/
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#define IS_SOONER(a, b, reference) \
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(((a) - (unsigned long)(reference)) < ((b) - (unsigned long)(reference)))
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/*
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* CATCHUP_INCREMENT, used when the function falls behind the counter.
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* Could be an increasing function instead of a constant;
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*/
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#define CATCHUP_INCREMENT 64
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static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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unsigned long flags;
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unsigned int mtflags;
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unsigned long timestamp, reference, previous;
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unsigned long nextcomp = 0L;
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int vpe = current_cpu_data.vpe_id;
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int cpu = smp_processor_id();
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local_irq_save(flags);
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mtflags = dmt();
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/*
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* Maintain the per-TC virtual timer
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* and program the per-VPE shared Count register
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* as appropriate here...
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*/
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reference = (unsigned long)read_c0_count();
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timestamp = MAKEVALID(reference + delta);
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/*
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* To really model the clock, we have to catch the case
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* where the current next-in-VPE timestamp is the old
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* timestamp for the calling CPE, but the new value is
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* in fact later. In that case, we have to do a full
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* scan and discover the new next-in-VPE CPU id and
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* timestamp.
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*/
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previous = smtc_nexttime[vpe][cpu];
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if (cpu == smtc_nextinvpe[vpe] && ISVALID(previous)
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&& IS_SOONER(previous, timestamp, reference)) {
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int i;
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int soonest = cpu;
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/*
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* Update timestamp array here, so that new
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* value gets considered along with those of
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* other virtual CPUs on the VPE.
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*/
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smtc_nexttime[vpe][cpu] = timestamp;
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for_each_online_cpu(i) {
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if (ISVALID(smtc_nexttime[vpe][i])
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&& IS_SOONER(smtc_nexttime[vpe][i],
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smtc_nexttime[vpe][soonest], reference)) {
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soonest = i;
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}
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}
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smtc_nextinvpe[vpe] = soonest;
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nextcomp = smtc_nexttime[vpe][soonest];
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/*
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* Otherwise, we don't have to process the whole array rank,
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* we just have to see if the event horizon has gotten closer.
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*/
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} else {
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if (!ISVALID(smtc_nexttime[vpe][smtc_nextinvpe[vpe]]) ||
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IS_SOONER(timestamp,
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smtc_nexttime[vpe][smtc_nextinvpe[vpe]], reference)) {
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smtc_nextinvpe[vpe] = cpu;
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nextcomp = timestamp;
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}
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/*
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* Since next-in-VPE may me the same as the executing
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* virtual CPU, we update the array *after* checking
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* its value.
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*/
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smtc_nexttime[vpe][cpu] = timestamp;
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}
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/*
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* It may be that, in fact, we don't need to update Compare,
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* but if we do, we want to make sure we didn't fall into
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* a crack just behind Count.
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*/
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if (ISVALID(nextcomp)) {
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write_c0_compare(nextcomp);
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ehb();
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/*
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* We never return an error, we just make sure
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* that we trigger the handlers as quickly as
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* we can if we fell behind.
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*/
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while ((nextcomp - (unsigned long)read_c0_count())
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> (unsigned long)LONG_MAX) {
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nextcomp += CATCHUP_INCREMENT;
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write_c0_compare(nextcomp);
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ehb();
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}
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}
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emt(mtflags);
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local_irq_restore(flags);
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return 0;
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}
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void smtc_distribute_timer(int vpe)
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{
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unsigned long flags;
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unsigned int mtflags;
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int cpu;
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struct clock_event_device *cd;
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unsigned long nextstamp;
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unsigned long reference;
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repeat:
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nextstamp = 0L;
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for_each_online_cpu(cpu) {
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/*
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* Find virtual CPUs within the current VPE who have
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* unserviced timer requests whose time is now past.
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*/
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local_irq_save(flags);
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mtflags = dmt();
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if (cpu_data[cpu].vpe_id == vpe &&
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ISVALID(smtc_nexttime[vpe][cpu])) {
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reference = (unsigned long)read_c0_count();
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if ((smtc_nexttime[vpe][cpu] - reference)
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> (unsigned long)LONG_MAX) {
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smtc_nexttime[vpe][cpu] = 0L;
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emt(mtflags);
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local_irq_restore(flags);
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/*
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* We don't send IPIs to ourself.
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*/
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if (cpu != smp_processor_id()) {
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smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
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} else {
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->event_handler(cd);
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}
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} else {
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/* Local to VPE but Valid Time not yet reached. */
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if (!ISVALID(nextstamp) ||
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IS_SOONER(smtc_nexttime[vpe][cpu], nextstamp,
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reference)) {
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smtc_nextinvpe[vpe] = cpu;
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nextstamp = smtc_nexttime[vpe][cpu];
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}
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emt(mtflags);
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local_irq_restore(flags);
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}
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} else {
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emt(mtflags);
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local_irq_restore(flags);
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}
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}
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/* Reprogram for interrupt at next soonest timestamp for VPE */
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if (ISVALID(nextstamp)) {
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write_c0_compare(nextstamp);
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ehb();
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if ((nextstamp - (unsigned long)read_c0_count())
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> (unsigned long)LONG_MAX)
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goto repeat;
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}
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}
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irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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/* If we're running SMTC, we've got MIPS MT and therefore MIPS32R2 */
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handle_perf_irq(1);
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if (read_c0_cause() & (1 << 30)) {
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/* Clear Count/Compare Interrupt */
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write_c0_compare(read_c0_compare());
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smtc_distribute_timer(cpu_data[cpu].vpe_id);
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}
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return IRQ_HANDLED;
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}
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int __cpuinit smtc_clockevent_init(void)
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{
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uint64_t mips_freq = mips_hpt_frequency;
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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unsigned int irq;
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int i;
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int j;
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if (!cpu_has_counter || !mips_hpt_frequency)
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return -ENXIO;
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if (cpu == 0) {
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for (i = 0; i < num_possible_cpus(); i++) {
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smtc_nextinvpe[i] = 0;
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for (j = 0; j < num_possible_cpus(); j++)
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smtc_nexttime[i][j] = 0L;
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}
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/*
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* SMTC also can't have the usablility test
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* run by secondary TCs once Compare is in use.
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*/
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if (!c0_compare_int_usable())
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return -ENXIO;
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}
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/*
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* With vectored interrupts things are getting platform specific.
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* get_c0_compare_int is a hook to allow a platform to return the
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* interrupt number of it's liking.
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*/
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irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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if (get_c0_compare_int)
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irq = get_c0_compare_int();
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->name = "MIPS";
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cd->features = CLOCK_EVT_FEAT_ONESHOT;
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/* Calculate the min / max delta */
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cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
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cd->shift = 32;
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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cd->rating = 300;
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cd->irq = irq;
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cd->cpumask = cpumask_of(cpu);
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cd->set_next_event = mips_next_event;
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cd->set_mode = mips_set_clock_mode;
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cd->event_handler = mips_event_handler;
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clockevents_register_device(cd);
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/*
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* On SMTC we only want to do the data structure
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* initialization and IRQ setup once.
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*/
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if (cpu)
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return 0;
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/*
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* And we need the hwmask associated with the c0_compare
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* vector to be initialized.
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*/
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irq_hwmask[irq] = (0x100 << cp0_compare_irq);
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if (cp0_timer_irq_installed)
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return 0;
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cp0_timer_irq_installed = 1;
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setup_irq(irq, &c0_compare_irqaction);
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return 0;
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}
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