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d6bb7a1ad3
gcc 4.2.1 for MN10300 is more agressive than the older gcc in reordering/moving other insns between an insn that sets flags and an insn that uses those flags. This leads to trouble with asm statements which are missing an explicit "cc" clobber. This patch adds the explicit "cc" clobber to asm statements which do indeed clobber the condition flags. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/* MN10300 64-bit division
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_DIV64
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#define _ASM_DIV64
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#include <linux/types.h>
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extern void ____unhandled_size_in_do_div___(void);
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/*
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* divide n by base, leaving the result in n and returning the remainder
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* - we can do this quite efficiently on the MN10300 by cascading the divides
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* through the MDR register
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*/
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#define do_div(n, base) \
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({ \
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unsigned __rem = 0; \
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if (sizeof(n) <= 4) { \
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asm("mov %1,mdr \n" \
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"divu %2,%0 \n" \
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"mov mdr,%1 \n" \
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: "+r"(n), "=d"(__rem) \
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: "r"(base), "1"(__rem) \
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: "cc" \
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); \
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} else if (sizeof(n) <= 8) { \
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union { \
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unsigned long long l; \
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u32 w[2]; \
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} __quot; \
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__quot.l = n; \
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asm("mov %0,mdr \n" /* MDR = 0 */ \
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"divu %3,%1 \n" \
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/* __quot.MSL = __div.MSL / base, */ \
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/* MDR = MDR:__div.MSL % base */ \
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"divu %3,%2 \n" \
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/* __quot.LSL = MDR:__div.LSL / base, */ \
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/* MDR = MDR:__div.LSL % base */ \
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"mov mdr,%0 \n" \
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: "=d"(__rem), "=r"(__quot.w[1]), "=r"(__quot.w[0]) \
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: "r"(base), "0"(__rem), "1"(__quot.w[1]), \
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"2"(__quot.w[0]) \
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: "cc" \
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); \
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n = __quot.l; \
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} else { \
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____unhandled_size_in_do_div___(); \
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} \
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__rem; \
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})
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/*
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* do an unsigned 32-bit multiply and divide with intermediate 64-bit product
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* so as not to lose accuracy
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* - we use the MDR register to hold the MSW of the product
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*/
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static inline __attribute__((const))
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unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div)
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{
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unsigned result;
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asm("mulu %2,%0 \n" /* MDR:val = val*mult */
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"divu %3,%0 \n" /* val = MDR:val/div;
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* MDR = MDR:val%div */
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: "=r"(result)
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: "0"(val), "ir"(mult), "r"(div)
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: "cc"
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);
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return result;
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}
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/*
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* do a signed 32-bit multiply and divide with intermediate 64-bit product so
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* as not to lose accuracy
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* - we use the MDR register to hold the MSW of the product
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*/
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static inline __attribute__((const))
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signed __muldiv64s(signed val, signed mult, signed div)
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{
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signed result;
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asm("mul %2,%0 \n" /* MDR:val = val*mult */
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"div %3,%0 \n" /* val = MDR:val/div;
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* MDR = MDR:val%div */
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: "=r"(result)
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: "0"(val), "ir"(mult), "r"(div)
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: "cc"
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);
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return result;
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}
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#endif /* _ASM_DIV64 */
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