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60253f100c
The currently supported minimum gcc version is 5.1. Before that, the PIC register, when generating Position Independent Code, was considered "fixed" in the sense that it wasn't in the set of registers available to the compiler's register allocator. Which, on x86-32, is already a very small set. What is more, the register allocator was unable to satisfy extended asm "=b" constraints. (Yes, PIC code uses %ebx on 32-bit as the base reg.) With gcc 5.1: "Reuse of the PIC hard register, instead of using a fixed register, was implemented on x86/x86-64 targets. This improves generated PIC code performance as more hard registers can be used. Shared libraries can significantly benefit from this optimization. Currently it is switched on only for x86/x86-64 targets. As RA infrastructure is already implemented for PIC register reuse, other targets might follow this in the future." (from: https://gcc.gnu.org/gcc-5/changes.html) which basically means that the register allocator has a higher degree of freedom when handling %ebx, including reloading it with the correct value before a PIC access. Furthermore: arch/x86/Makefile: # Never want PIC in a 32-bit kernel, prevent breakage with GCC built # with nonstandard options KBUILD_CFLAGS += -fno-pic $ gcc -Wp,-MMD,arch/x86/boot/.cpuflags.o.d ... -fno-pic ... -D__KBUILD_MODNAME=kmod_cpuflags -c -o arch/x86/boot/cpuflags.o arch/x86/boot/cpuflags.c so the 32-bit workaround in cpuid_count() is fixing exactly nothing because 32-bit configs don't even allow PIC builds. As to 64-bit builds: they're done using -mcmodel=kernel which produces RIP-relative addressing for PIC builds and thus does not apply here either. So get rid of the thing and make cpuid_count() nice and simple. There should be no functional changes resulting from this. [ bp: Expand commit message. ] Signed-off-by: Uros Bizjak <ubizjak@gmail.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/20221104124546.196077-1-ubizjak@gmail.com
119 lines
2.6 KiB
C
119 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/types.h>
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#include "bitops.h"
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#include <asm/processor-flags.h>
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#include <asm/required-features.h>
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#include <asm/msr-index.h>
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#include "cpuflags.h"
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struct cpu_features cpu;
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u32 cpu_vendor[3];
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static bool loaded_flags;
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static int has_fpu(void)
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{
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u16 fcw = -1, fsw = -1;
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unsigned long cr0;
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asm volatile("mov %%cr0,%0" : "=r" (cr0));
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if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
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cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
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asm volatile("mov %0,%%cr0" : : "r" (cr0));
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}
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asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
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: "+m" (fsw), "+m" (fcw));
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return fsw == 0 && (fcw & 0x103f) == 0x003f;
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}
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/*
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* For building the 16-bit code we want to explicitly specify 32-bit
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* push/pop operations, rather than just saying 'pushf' or 'popf' and
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* letting the compiler choose. But this is also included from the
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* compressed/ directory where it may be 64-bit code, and thus needs
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* to be 'pushfq' or 'popfq' in that case.
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*/
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#ifdef __x86_64__
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#define PUSHF "pushfq"
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#define POPF "popfq"
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#else
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#define PUSHF "pushfl"
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#define POPF "popfl"
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#endif
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int has_eflag(unsigned long mask)
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{
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unsigned long f0, f1;
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asm volatile(PUSHF " \n\t"
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PUSHF " \n\t"
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"pop %0 \n\t"
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"mov %0,%1 \n\t"
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"xor %2,%1 \n\t"
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"push %1 \n\t"
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POPF " \n\t"
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PUSHF " \n\t"
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"pop %1 \n\t"
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POPF
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: "=&r" (f0), "=&r" (f1)
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: "ri" (mask));
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return !!((f0^f1) & mask);
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}
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void cpuid_count(u32 id, u32 count, u32 *a, u32 *b, u32 *c, u32 *d)
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{
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asm volatile("cpuid"
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: "=a" (*a), "=b" (*b), "=c" (*c), "=d" (*d)
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: "0" (id), "2" (count)
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);
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}
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#define cpuid(id, a, b, c, d) cpuid_count(id, 0, a, b, c, d)
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void get_cpuflags(void)
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{
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u32 max_intel_level, max_amd_level;
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u32 tfms;
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u32 ignored;
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if (loaded_flags)
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return;
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loaded_flags = true;
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if (has_fpu())
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set_bit(X86_FEATURE_FPU, cpu.flags);
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if (has_eflag(X86_EFLAGS_ID)) {
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cpuid(0x0, &max_intel_level, &cpu_vendor[0], &cpu_vendor[2],
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&cpu_vendor[1]);
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if (max_intel_level >= 0x00000001 &&
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max_intel_level <= 0x0000ffff) {
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cpuid(0x1, &tfms, &ignored, &cpu.flags[4],
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&cpu.flags[0]);
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cpu.level = (tfms >> 8) & 15;
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cpu.family = cpu.level;
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cpu.model = (tfms >> 4) & 15;
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if (cpu.level >= 6)
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cpu.model += ((tfms >> 16) & 0xf) << 4;
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}
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if (max_intel_level >= 0x00000007) {
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cpuid_count(0x00000007, 0, &ignored, &ignored,
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&cpu.flags[16], &ignored);
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}
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cpuid(0x80000000, &max_amd_level, &ignored, &ignored,
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&ignored);
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if (max_amd_level >= 0x80000001 &&
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max_amd_level <= 0x8000ffff) {
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cpuid(0x80000001, &ignored, &ignored, &cpu.flags[6],
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&cpu.flags[1]);
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}
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}
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}
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