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![Christoph Hellwig](/assets/img/avatar_default.png)
Signed-off-by: Christoph Hellwig <hch@lst.de> Cc: marc.zyngier@arm.com Cc: antoine.tenart@free-electrons.com Cc: jason@lakedaemon.net Cc: tsahee@annapurnalabs.com Link: http://lkml.kernel.org/r/1462459265-20974-1-git-send-email-hch@lst.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
293 lines
7 KiB
C
293 lines
7 KiB
C
/*
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* Annapurna Labs MSIX support services
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*
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* Copyright (C) 2016, Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Antoine Tenart <antoine.tenart@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <asm/irq.h>
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#include <asm/msi.h>
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/* MSIX message address format: local GIC target */
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#define ALPINE_MSIX_SPI_TARGET_CLUSTER0 BIT(16)
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struct alpine_msix_data {
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spinlock_t msi_map_lock;
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phys_addr_t addr;
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u32 spi_first; /* The SGI number that MSIs start */
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u32 num_spis; /* The number of SGIs for MSIs */
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unsigned long *msi_map;
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};
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static void alpine_msix_mask_msi_irq(struct irq_data *d)
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{
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static void alpine_msix_unmask_msi_irq(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip alpine_msix_irq_chip = {
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.name = "MSIx",
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.irq_mask = alpine_msix_mask_msi_irq,
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.irq_unmask = alpine_msix_unmask_msi_irq,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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};
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static int alpine_msix_allocate_sgi(struct alpine_msix_data *priv, int num_req)
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{
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int first;
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spin_lock(&priv->msi_map_lock);
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first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0,
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num_req, 0);
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if (first >= priv->num_spis) {
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spin_unlock(&priv->msi_map_lock);
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return -ENOSPC;
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}
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bitmap_set(priv->msi_map, first, num_req);
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spin_unlock(&priv->msi_map_lock);
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return priv->spi_first + first;
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}
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static void alpine_msix_free_sgi(struct alpine_msix_data *priv, unsigned sgi,
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int num_req)
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{
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int first = sgi - priv->spi_first;
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spin_lock(&priv->msi_map_lock);
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bitmap_clear(priv->msi_map, first, num_req);
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spin_unlock(&priv->msi_map_lock);
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}
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static void alpine_msix_compose_msi_msg(struct irq_data *data,
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struct msi_msg *msg)
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{
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struct alpine_msix_data *priv = irq_data_get_irq_chip_data(data);
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phys_addr_t msg_addr = priv->addr;
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msg_addr |= (data->hwirq << 3);
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msg->address_hi = upper_32_bits(msg_addr);
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msg->address_lo = lower_32_bits(msg_addr);
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msg->data = 0;
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}
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static struct msi_domain_info alpine_msix_domain_info = {
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.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX,
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.chip = &alpine_msix_irq_chip,
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};
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static struct irq_chip middle_irq_chip = {
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.name = "alpine_msix_middle",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_compose_msi_msg = alpine_msix_compose_msi_msg,
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};
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static int alpine_msix_gic_domain_alloc(struct irq_domain *domain,
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unsigned int virq, int sgi)
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{
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struct irq_fwspec fwspec;
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struct irq_data *d;
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int ret;
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if (!is_of_node(domain->parent->fwnode))
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return -EINVAL;
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 3;
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fwspec.param[0] = 0;
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fwspec.param[1] = sgi;
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fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
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ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (ret)
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return ret;
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d = irq_domain_get_irq_data(domain->parent, virq);
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d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
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return 0;
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}
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static int alpine_msix_middle_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct alpine_msix_data *priv = domain->host_data;
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int sgi, err, i;
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sgi = alpine_msix_allocate_sgi(priv, nr_irqs);
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if (sgi < 0)
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return sgi;
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for (i = 0; i < nr_irqs; i++) {
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err = alpine_msix_gic_domain_alloc(domain, virq + i, sgi + i);
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if (err)
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goto err_sgi;
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irq_domain_set_hwirq_and_chip(domain, virq + i, sgi + i,
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&middle_irq_chip, priv);
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}
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return 0;
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err_sgi:
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while (--i >= 0)
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irq_domain_free_irqs_parent(domain, virq, i);
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alpine_msix_free_sgi(priv, sgi, nr_irqs);
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return err;
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}
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static void alpine_msix_middle_domain_free(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct alpine_msix_data *priv = irq_data_get_irq_chip_data(d);
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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alpine_msix_free_sgi(priv, d->hwirq, nr_irqs);
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}
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static const struct irq_domain_ops alpine_msix_middle_domain_ops = {
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.alloc = alpine_msix_middle_domain_alloc,
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.free = alpine_msix_middle_domain_free,
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};
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static int alpine_msix_init_domains(struct alpine_msix_data *priv,
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struct device_node *node)
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{
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struct irq_domain *middle_domain, *msi_domain, *gic_domain;
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struct device_node *gic_node;
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gic_node = of_irq_find_parent(node);
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if (!gic_node) {
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pr_err("Failed to find the GIC node\n");
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return -ENODEV;
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}
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gic_domain = irq_find_host(gic_node);
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if (!gic_domain) {
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pr_err("Failed to find the GIC domain\n");
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return -ENXIO;
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}
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middle_domain = irq_domain_add_tree(NULL,
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&alpine_msix_middle_domain_ops,
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priv);
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if (!middle_domain) {
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pr_err("Failed to create the MSIX middle domain\n");
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return -ENOMEM;
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}
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middle_domain->parent = gic_domain;
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msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
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&alpine_msix_domain_info,
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middle_domain);
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if (!msi_domain) {
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pr_err("Failed to create MSI domain\n");
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irq_domain_remove(middle_domain);
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return -ENOMEM;
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}
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return 0;
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}
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static int alpine_msix_init(struct device_node *node,
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struct device_node *parent)
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{
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struct alpine_msix_data *priv;
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struct resource res;
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int ret;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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spin_lock_init(&priv->msi_map_lock);
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ret = of_address_to_resource(node, 0, &res);
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if (ret) {
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pr_err("Failed to allocate resource\n");
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goto err_priv;
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}
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/*
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* The 20 least significant bits of addr provide direct information
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* regarding the interrupt destination.
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*
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* To select the primary GIC as the target GIC, bits [18:17] must be set
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* to 0x0. In this case, bit 16 (SPI_TARGET_CLUSTER0) must be set.
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*/
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priv->addr = res.start & GENMASK_ULL(63,20);
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priv->addr |= ALPINE_MSIX_SPI_TARGET_CLUSTER0;
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if (of_property_read_u32(node, "al,msi-base-spi", &priv->spi_first)) {
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pr_err("Unable to parse MSI base\n");
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ret = -EINVAL;
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goto err_priv;
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}
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if (of_property_read_u32(node, "al,msi-num-spis", &priv->num_spis)) {
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pr_err("Unable to parse MSI numbers\n");
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ret = -EINVAL;
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goto err_priv;
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}
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priv->msi_map = kzalloc(sizeof(*priv->msi_map) * BITS_TO_LONGS(priv->num_spis),
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GFP_KERNEL);
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if (!priv->msi_map) {
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ret = -ENOMEM;
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goto err_priv;
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}
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pr_debug("Registering %d msixs, starting at %d\n",
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priv->num_spis, priv->spi_first);
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ret = alpine_msix_init_domains(priv, node);
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if (ret)
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goto err_map;
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return 0;
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err_map:
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kfree(priv->msi_map);
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err_priv:
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kfree(priv);
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return ret;
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}
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IRQCHIP_DECLARE(alpine_msix, "al,alpine-msix", alpine_msix_init);
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