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![Masahiro Yamada](/assets/img/avatar_default.png)
Kernel source files need not include <linux/kconfig.h> explicitly because the top Makefile forces to include it with: -include $(srctree)/include/linux/kconfig.h This commit removes explicit includes except the following: * arch/s390/include/asm/facilities_src.h * tools/testing/radix-tree/linux/kernel.h These two are used for host programs. Link: http://lkml.kernel.org/r/1473656164-11929-1-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
214 lines
5.6 KiB
C
214 lines
5.6 KiB
C
/*
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* Generic Broadcom Set Top Box Level 2 Interrupt controller driver
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*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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/* Register offsets in the L2 interrupt controller */
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#define CPU_STATUS 0x00
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#define CPU_SET 0x04
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#define CPU_CLEAR 0x08
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#define CPU_MASK_STATUS 0x0c
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#define CPU_MASK_SET 0x10
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#define CPU_MASK_CLEAR 0x14
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/* L2 intc private data structure */
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struct brcmstb_l2_intc_data {
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int parent_irq;
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void __iomem *base;
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struct irq_domain *domain;
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bool can_wake;
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u32 saved_mask; /* for suspend/resume */
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};
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static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
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{
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struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(b->domain, 0);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int irq;
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u32 status;
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chained_irq_enter(chip, desc);
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status = irq_reg_readl(gc, CPU_STATUS) &
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~(irq_reg_readl(gc, CPU_MASK_STATUS));
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if (status == 0) {
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raw_spin_lock(&desc->lock);
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handle_bad_irq(desc);
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raw_spin_unlock(&desc->lock);
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goto out;
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}
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do {
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irq = ffs(status) - 1;
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/* ack at our level */
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irq_reg_writel(gc, 1 << irq, CPU_CLEAR);
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status &= ~(1 << irq);
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generic_handle_irq(irq_find_mapping(b->domain, irq));
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} while (status);
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out:
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chained_irq_exit(chip, desc);
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}
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static void brcmstb_l2_intc_suspend(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_l2_intc_data *b = gc->private;
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irq_gc_lock(gc);
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/* Save the current mask */
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b->saved_mask = irq_reg_readl(gc, CPU_MASK_STATUS);
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if (b->can_wake) {
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/* Program the wakeup mask */
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irq_reg_writel(gc, ~gc->wake_active, CPU_MASK_SET);
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irq_reg_writel(gc, gc->wake_active, CPU_MASK_CLEAR);
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}
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irq_gc_unlock(gc);
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}
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static void brcmstb_l2_intc_resume(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_l2_intc_data *b = gc->private;
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irq_gc_lock(gc);
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/* Clear unmasked non-wakeup interrupts */
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irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, CPU_CLEAR);
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/* Restore the saved mask */
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irq_reg_writel(gc, b->saved_mask, CPU_MASK_SET);
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irq_reg_writel(gc, ~b->saved_mask, CPU_MASK_CLEAR);
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irq_gc_unlock(gc);
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}
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static int __init brcmstb_l2_intc_of_init(struct device_node *np,
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struct device_node *parent)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct brcmstb_l2_intc_data *data;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int ret;
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unsigned int flags;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->base = of_iomap(np, 0);
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if (!data->base) {
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pr_err("failed to remap intc L2 registers\n");
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ret = -ENOMEM;
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goto out_free;
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}
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/* Disable all interrupts by default */
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writel(0xffffffff, data->base + CPU_MASK_SET);
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/* Wakeup interrupts may be retained from S5 (cold boot) */
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data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
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if (!data->can_wake)
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writel(0xffffffff, data->base + CPU_CLEAR);
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data->parent_irq = irq_of_parse_and_map(np, 0);
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if (!data->parent_irq) {
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pr_err("failed to find parent interrupt\n");
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ret = -EINVAL;
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goto out_unmap;
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}
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data->domain = irq_domain_add_linear(np, 32,
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&irq_generic_chip_ops, NULL);
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if (!data->domain) {
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ret = -ENOMEM;
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goto out_unmap;
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}
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/* MIPS chips strapped for BE will automagically configure the
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* peripheral registers for CPU-native byte order.
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*/
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flags = 0;
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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flags |= IRQ_GC_BE_IO;
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/* Allocate a single Generic IRQ chip for this node */
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ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
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np->full_name, handle_edge_irq, clr, 0, flags);
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if (ret) {
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pr_err("failed to allocate generic irq chip\n");
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goto out_free_domain;
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}
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/* Set the IRQ chaining logic */
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irq_set_chained_handler_and_data(data->parent_irq,
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brcmstb_l2_intc_irq_handle, data);
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gc = irq_get_domain_generic_chip(data->domain, 0);
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gc->reg_base = data->base;
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gc->private = data;
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->regs.ack = CPU_CLEAR;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->regs.disable = CPU_MASK_SET;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->regs.enable = CPU_MASK_CLEAR;
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ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
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ct->chip.irq_resume = brcmstb_l2_intc_resume;
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if (data->can_wake) {
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/* This IRQ chip can wake the system, set all child interrupts
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* in wake_enabled mask
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*/
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gc->wake_enabled = 0xffffffff;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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}
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pr_info("registered L2 intc (mem: 0x%p, parent irq: %d)\n",
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data->base, data->parent_irq);
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return 0;
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out_free_domain:
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irq_domain_remove(data->domain);
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out_unmap:
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iounmap(data->base);
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out_free:
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kfree(data);
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return ret;
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}
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IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_intc_of_init);
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