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e87d2db2a2
The eSDHC_PRSSTAT[SDSTB] bit indicates whether the internal card clock is stable. This bit is for the host driver to poll clock status when changing the clock frequency. It is recommended to clear eSDHC_SYSCTL[SDCLKEN] to remove glitch on the card clock when the frequency is changing. This patch is to disable SDCLKEN bit before changing frequency and enable it after SDSTB bit is set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
/*
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* Freescale eSDHC controller driver generics for OF and pltfm.
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Copyright (c) 2010 Pengutronix e.K.
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* Author: Wolfram Sang <w.sang@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
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#define _DRIVERS_MMC_SDHCI_ESDHC_H
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/*
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* Ops and quirks for the Freescale eSDHC controller.
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*/
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#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
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SDHCI_QUIRK_NO_BUSY_IRQ | \
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
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SDHCI_QUIRK_PIO_NEEDS_DELAY | \
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SDHCI_QUIRK_NO_HISPD_BIT)
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/* pltfm-specific */
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#define ESDHC_HOST_CONTROL_LE 0x20
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/*
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* eSDHC register definition
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*/
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/* Present State Register */
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#define ESDHC_PRSSTAT 0x24
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#define ESDHC_CLOCK_STABLE 0x00000008
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/* Protocol Control Register */
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#define ESDHC_PROCTL 0x28
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#define ESDHC_CTRL_4BITBUS (0x1 << 1)
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#define ESDHC_CTRL_8BITBUS (0x2 << 1)
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#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
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#define ESDHC_HOST_CONTROL_RES 0x01
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/* System Control Register */
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#define ESDHC_SYSTEM_CONTROL 0x2c
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#define ESDHC_CLOCK_MASK 0x0000fff0
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#define ESDHC_PREDIV_SHIFT 8
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#define ESDHC_DIVIDER_SHIFT 4
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#define ESDHC_CLOCK_SDCLKEN 0x00000008
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#define ESDHC_CLOCK_PEREN 0x00000004
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#define ESDHC_CLOCK_HCKEN 0x00000002
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#define ESDHC_CLOCK_IPGEN 0x00000001
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/* Control Register for DMA transfer */
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#define ESDHC_DMA_SYSCTL 0x40c
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#define ESDHC_DMA_SNOOP 0x00000040
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#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
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