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8a1b82d744
Add register sequences for PCIe + QSGMII PHY multilink configuration. PHY configuration for multi-link operation is done in two steps. e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes. Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below. [1] For first step, the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc]. This will configure PHY registers associated for PCIe involving PLLLC registers and registers for first 2 lanes of PHY. [2] In second step, the register values are selected as [TYPE_QSGMII][TYPE_PCIE][ssc]. This will configure PHY registers associated for QSGMII involving PLLLC1 registers and registers for other 2 lanes of PHY. This completes the PHY configuration for multilink operation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-14-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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allwinner | ||
amlogic | ||
broadcom | ||
cadence | ||
freescale | ||
hisilicon | ||
ingenic | ||
intel | ||
lantiq | ||
marvell | ||
mediatek | ||
microchip | ||
motorola | ||
mscc | ||
qualcomm | ||
ralink | ||
renesas | ||
rockchip | ||
samsung | ||
socionext | ||
st | ||
tegra | ||
ti | ||
xilinx | ||
Kconfig | ||
Makefile | ||
phy-can-transceiver.c | ||
phy-core-mipi-dphy.c | ||
phy-core.c | ||
phy-lgm-usb.c | ||
phy-lpc18xx-usb-otg.c | ||
phy-pistachio-usb.c | ||
phy-xgene.c |