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![Lukas Bulwahn](/assets/img/avatar_default.png)
Commit fa41d10589
("fpga: dfl-pci: locate DFLs by PCIe vendor specific
capability") provides documentation to the FPGA Device Feature List (DFL)
Framework Overview, but introduced new documentation warnings:
./Documentation/fpga/dfl.rst:
505: WARNING: Title underline too short.
523: WARNING: Unexpected indentation.
523: WARNING: Blank line required after table.
524: WARNING: Block quote ends without a blank line; unexpected unindent.
Rectify ReST formatting in ./Documentation/fpga/dfl.rst.
Tested-by: Tom Rix <trix@redhat.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
Acked-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20210111112113.27242-1-lukas.bulwahn@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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ReStructuredText
537 lines
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ReStructuredText
=================================================
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FPGA Device Feature List (DFL) Framework Overview
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=================================================
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Authors:
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- Enno Luebbers <enno.luebbers@intel.com>
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- Xiao Guangrong <guangrong.xiao@linux.intel.com>
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- Wu Hao <hao.wu@intel.com>
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The Device Feature List (DFL) FPGA framework (and drivers according to
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this framework) hides the very details of low layer hardwares and provides
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unified interfaces to userspace. Applications could use these interfaces to
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configure, enumerate, open and access FPGA accelerators on platforms which
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implement the DFL in the device memory. Besides this, the DFL framework
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enables system level management functions such as FPGA reconfiguration.
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Device Feature List (DFL) Overview
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==================================
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Device Feature List (DFL) defines a linked list of feature headers within the
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device MMIO space to provide an extensible way of adding features. Software can
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walk through these predefined data structures to enumerate FPGA features:
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FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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as illustrated below::
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Header Header Header Header
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+----------+ +-->+----------+ +-->+----------+ +-->+----------+
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| Type | | | Type | | | Type | | | Type |
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| FIU | | | Private | | | Private | | | Private |
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+----------+ | | Feature | | | Feature | | | Feature |
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| Next_DFH |--+ +----------+ | +----------+ | +----------+
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+----------+ | Next_DFH |--+ | Next_DFH |--+ | Next_DFH |--> NULL
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| ID | +----------+ +----------+ +----------+
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+----------+ | ID | | ID | | ID |
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| Next_AFU |--+ +----------+ +----------+ +----------+
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+----------+ | | Feature | | Feature | | Feature |
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| Header | | | Register | | Register | | Register |
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| Register | | | Set | | Set | | Set |
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| Set | | +----------+ +----------+ +----------+
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+----------+ | Header
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+-->+----------+
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| Type |
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| AFU |
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+----------+
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| Next_DFH |--> NULL
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+----------+
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| GUID |
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+----------+
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| Header |
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| Register |
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| Set |
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+----------+
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FPGA Interface Unit (FIU) represents a standalone functional unit for the
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interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
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descriptions on FME and Port in later sections).
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Accelerated Function Unit (AFU) represents a FPGA programmable region and
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always connects to a FIU (e.g. a Port) as its child as illustrated above.
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Private Features represent sub features of the FIU and AFU. They could be
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various function blocks with different IDs, but all private features which
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belong to the same FIU or AFU, must be linked to one list via the Next Device
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Feature Header (Next_DFH) pointer.
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Each FIU, AFU and Private Feature could implement its own functional registers.
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The functional register set for FIU and AFU, is named as Header Register Set,
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e.g. FME Header Register Set, and the one for Private Feature, is named as
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Feature Register Set, e.g. FME Partial Reconfiguration Feature Register Set.
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This Device Feature List provides a way of linking features together, it's
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convenient for software to locate each feature by walking through this list,
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and can be implemented in register regions of any FPGA device.
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FIU - FME (FPGA Management Engine)
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==================================
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The FPGA Management Engine performs reconfiguration and other infrastructure
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functions. Each FPGA device only has one FME.
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User-space applications can acquire exclusive access to the FME using open(),
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and release it using close().
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The following functions are exposed through ioctls:
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- Get driver API version (DFL_FPGA_GET_API_VERSION)
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- Check for extensions (DFL_FPGA_CHECK_EXTENSION)
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- Program bitstream (DFL_FPGA_FME_PORT_PR)
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- Assign port to PF (DFL_FPGA_FME_PORT_ASSIGN)
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- Release port from PF (DFL_FPGA_FME_PORT_RELEASE)
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- Get number of irqs of FME global error (DFL_FPGA_FME_ERR_GET_IRQ_NUM)
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- Set interrupt trigger for FME error (DFL_FPGA_FME_ERR_SET_IRQ)
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More functions are exposed through sysfs
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(/sys/class/fpga_region/regionX/dfl-fme.n/):
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Read bitstream ID (bitstream_id)
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bitstream_id indicates version of the static FPGA region.
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Read bitstream metadata (bitstream_metadata)
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bitstream_metadata includes detailed information of static FPGA region,
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e.g. synthesis date and seed.
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Read number of ports (ports_num)
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one FPGA device may have more than one port, this sysfs interface indicates
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how many ports the FPGA device has.
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Global error reporting management (errors/)
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error reporting sysfs interfaces allow user to read errors detected by the
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hardware, and clear the logged errors.
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Power management (dfl_fme_power hwmon)
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power management hwmon sysfs interfaces allow user to read power management
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information (power consumption, thresholds, threshold status, limits, etc.)
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and configure power thresholds for different throttling levels.
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Thermal management (dfl_fme_thermal hwmon)
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thermal management hwmon sysfs interfaces allow user to read thermal
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management information (current temperature, thresholds, threshold status,
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etc.).
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Performance reporting
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performance counters are exposed through perf PMU APIs. Standard perf tool
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can be used to monitor all available perf events. Please see performance
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counter section below for more detailed information.
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FIU - PORT
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==========
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A port represents the interface between the static FPGA fabric and a partially
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reconfigurable region containing an AFU. It controls the communication from SW
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to the accelerator and exposes features such as reset and debug. Each FPGA
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device may have more than one port, but always one AFU per port.
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AFU
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===
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An AFU is attached to a port FIU and exposes a fixed length MMIO region to be
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used for accelerator-specific control registers.
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User-space applications can acquire exclusive access to an AFU attached to a
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port by using open() on the port device node and release it using close().
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The following functions are exposed through ioctls:
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- Get driver API version (DFL_FPGA_GET_API_VERSION)
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- Check for extensions (DFL_FPGA_CHECK_EXTENSION)
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- Get port info (DFL_FPGA_PORT_GET_INFO)
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- Get MMIO region info (DFL_FPGA_PORT_GET_REGION_INFO)
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- Map DMA buffer (DFL_FPGA_PORT_DMA_MAP)
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- Unmap DMA buffer (DFL_FPGA_PORT_DMA_UNMAP)
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- Reset AFU (DFL_FPGA_PORT_RESET)
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- Get number of irqs of port error (DFL_FPGA_PORT_ERR_GET_IRQ_NUM)
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- Set interrupt trigger for port error (DFL_FPGA_PORT_ERR_SET_IRQ)
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- Get number of irqs of UINT (DFL_FPGA_PORT_UINT_GET_IRQ_NUM)
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- Set interrupt trigger for UINT (DFL_FPGA_PORT_UINT_SET_IRQ)
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DFL_FPGA_PORT_RESET:
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reset the FPGA Port and its AFU. Userspace can do Port
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reset at any time, e.g. during DMA or Partial Reconfiguration. But it should
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never cause any system level issue, only functional failure (e.g. DMA or PR
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operation failure) and be recoverable from the failure.
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User-space applications can also mmap() accelerator MMIO regions.
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More functions are exposed through sysfs:
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(/sys/class/fpga_region/<regionX>/<dfl-port.m>/):
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Read Accelerator GUID (afu_id)
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afu_id indicates which PR bitstream is programmed to this AFU.
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Error reporting (errors/)
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error reporting sysfs interfaces allow user to read port/afu errors
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detected by the hardware, and clear the logged errors.
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DFL Framework Overview
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======================
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::
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+----------+ +--------+ +--------+ +--------+
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| FME | | AFU | | AFU | | AFU |
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| Module | | Module | | Module | | Module |
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+----------+ +--------+ +--------+ +--------+
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+-----------------------+
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| FPGA Container Device | Device Feature List
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| (FPGA Base Region) | Framework
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+-----------------------+
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------------------------------------------------------------------
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+----------------------------+
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| FPGA DFL Device Module |
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| (e.g. PCIE/Platform Device)|
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+----------------------------+
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+------------------------+
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| FPGA Hardware Device |
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+------------------------+
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DFL framework in kernel provides common interfaces to create container device
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(FPGA base region), discover feature devices and their private features from the
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given Device Feature Lists and create platform devices for feature devices
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(e.g. FME, Port and AFU) with related resources under the container device. It
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also abstracts operations for the private features and exposes common ops to
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feature device drivers.
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The FPGA DFL Device could be different hardwares, e.g. PCIe device, platform
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device and etc. Its driver module is always loaded first once the device is
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created by the system. This driver plays an infrastructural role in the
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driver architecture. It locates the DFLs in the device memory, handles them
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and related resources to common interfaces from DFL framework for enumeration.
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(Please refer to drivers/fpga/dfl.c for detailed enumeration APIs).
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The FPGA Management Engine (FME) driver is a platform driver which is loaded
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automatically after FME platform device creation from the DFL device module. It
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provides the key features for FPGA management, including:
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a) Expose static FPGA region information, e.g. version and metadata.
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Users can read related information via sysfs interfaces exposed
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by FME driver.
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b) Partial Reconfiguration. The FME driver creates FPGA manager, FPGA
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bridges and FPGA regions during PR sub feature initialization. Once
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it receives a DFL_FPGA_FME_PORT_PR ioctl from user, it invokes the
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common interface function from FPGA Region to complete the partial
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reconfiguration of the PR bitstream to the given port.
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Similar to the FME driver, the FPGA Accelerated Function Unit (AFU) driver is
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probed once the AFU platform device is created. The main function of this module
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is to provide an interface for userspace applications to access the individual
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accelerators, including basic reset control on port, AFU MMIO region export, dma
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buffer mapping service functions.
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After feature platform devices creation, matched platform drivers will be loaded
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automatically to handle different functionalities. Please refer to next sections
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for detailed information on functional units which have been already implemented
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under this DFL framework.
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Partial Reconfiguration
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=======================
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As mentioned above, accelerators can be reconfigured through partial
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reconfiguration of a PR bitstream file. The PR bitstream file must have been
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generated for the exact static FPGA region and targeted reconfigurable region
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(port) of the FPGA, otherwise, the reconfiguration operation will fail and
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possibly cause system instability. This compatibility can be checked by
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comparing the compatibility ID noted in the header of PR bitstream file against
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the compat_id exposed by the target FPGA region. This check is usually done by
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userspace before calling the reconfiguration IOCTL.
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FPGA virtualization - PCIe SRIOV
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================================
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This section describes the virtualization support on DFL based FPGA device to
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enable accessing an accelerator from applications running in a virtual machine
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(VM). This section only describes the PCIe based FPGA device with SRIOV support.
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Features supported by the particular FPGA device are exposed through Device
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Feature Lists, as illustrated below:
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::
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+-------------------------------+ +-------------+
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| PF | | VF |
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+-------------------------------+ +-------------+
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^ ^ ^ ^
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| | | |
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+-----|------------|---------|--------------|-------+
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| | | | | |
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| +-----+ +-------+ +-------+ +-------+ |
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| | FME | | Port0 | | Port1 | | Port2 | |
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| +-----+ +-------+ +-------+ +-------+ |
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| ^ ^ ^ |
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| | | | |
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| +-------+ +------+ +-------+ |
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| | AFU | | AFU | | AFU | |
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| +-------+ +------+ +-------+ |
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| DFL based FPGA PCIe Device |
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+---------------------------------------------------+
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FME is always accessed through the physical function (PF).
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Ports (and related AFUs) are accessed via PF by default, but could be exposed
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through virtual function (VF) devices via PCIe SRIOV. Each VF only contains
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1 Port and 1 AFU for isolation. Users could assign individual VFs (accelerators)
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created via PCIe SRIOV interface, to virtual machines.
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The driver organization in virtualization case is illustrated below:
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::
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+-------++------++------+ |
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| FME || FME || FME | |
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| FPGA || FPGA || FPGA | |
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|Manager||Bridge||Region| |
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+-------++------++------+ |
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+-----------------------+ +--------+ | +--------+
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| FME | | AFU | | | AFU |
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| Module | | Module | | | Module |
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+-----------------------+ +--------+ | +--------+
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+-----------------------+ | +-----------------------+
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| FPGA Container Device | | | FPGA Container Device |
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| (FPGA Base Region) | | | (FPGA Base Region) |
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+-----------------------+ | +-----------------------+
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+------------------+ | +------------------+
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| FPGA PCIE Module | | Virtual | FPGA PCIE Module |
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+------------------+ Host | Machine +------------------+
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-------------------------------------- | ------------------------------
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+---------------+ | +---------------+
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| PCI PF Device | | | PCI VF Device |
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+---------------+ | +---------------+
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FPGA PCIe device driver is always loaded first once a FPGA PCIe PF or VF device
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is detected. It:
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* Finishes enumeration on both FPGA PCIe PF and VF device using common
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interfaces from DFL framework.
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* Supports SRIOV.
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The FME device driver plays a management role in this driver architecture, it
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provides ioctls to release Port from PF and assign Port to PF. After release
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a port from PF, then it's safe to expose this port through a VF via PCIe SRIOV
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sysfs interface.
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To enable accessing an accelerator from applications running in a VM, the
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respective AFU's port needs to be assigned to a VF using the following steps:
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#. The PF owns all AFU ports by default. Any port that needs to be
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reassigned to a VF must first be released through the
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DFL_FPGA_FME_PORT_RELEASE ioctl on the FME device.
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#. Once N ports are released from PF, then user can use command below
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to enable SRIOV and VFs. Each VF owns only one Port with AFU.
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::
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echo N > $PCI_DEVICE_PATH/sriov_numvfs
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#. Pass through the VFs to VMs
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#. The AFU under VF is accessible from applications in VM (using the
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same driver inside the VF).
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Note that an FME can't be assigned to a VF, thus PR and other management
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functions are only available via the PF.
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Device enumeration
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==================
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This section introduces how applications enumerate the fpga device from
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the sysfs hierarchy under /sys/class/fpga_region.
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In the example below, two DFL based FPGA devices are installed in the host. Each
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fpga device has one FME and two ports (AFUs).
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FPGA regions are created under /sys/class/fpga_region/::
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/sys/class/fpga_region/region0
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/sys/class/fpga_region/region1
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/sys/class/fpga_region/region2
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...
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Application needs to search each regionX folder, if feature device is found,
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(e.g. "dfl-port.n" or "dfl-fme.m" is found), then it's the base
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fpga region which represents the FPGA device.
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Each base region has one FME and two ports (AFUs) as child devices::
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/sys/class/fpga_region/region0/dfl-fme.0
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/sys/class/fpga_region/region0/dfl-port.0
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/sys/class/fpga_region/region0/dfl-port.1
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...
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/sys/class/fpga_region/region3/dfl-fme.1
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/sys/class/fpga_region/region3/dfl-port.2
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/sys/class/fpga_region/region3/dfl-port.3
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...
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In general, the FME/AFU sysfs interfaces are named as follows::
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/sys/class/fpga_region/<regionX>/<dfl-fme.n>/
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/sys/class/fpga_region/<regionX>/<dfl-port.m>/
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with 'n' consecutively numbering all FMEs and 'm' consecutively numbering all
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ports.
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The device nodes used for ioctl() or mmap() can be referenced through::
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/sys/class/fpga_region/<regionX>/<dfl-fme.n>/dev
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/sys/class/fpga_region/<regionX>/<dfl-port.n>/dev
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Performance Counters
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====================
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Performance reporting is one private feature implemented in FME. It could
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supports several independent, system-wide, device counter sets in hardware to
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monitor and count for performance events, including "basic", "cache", "fabric",
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"vtd" and "vtd_sip" counters. Users could use standard perf tool to monitor
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FPGA cache hit/miss rate, transaction number, interface clock counter of AFU
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and other FPGA performance events.
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Different FPGA devices may have different counter sets, depending on hardware
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implementation. E.g., some discrete FPGA cards don't have any cache. User could
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use "perf list" to check which perf events are supported by target hardware.
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In order to allow user to use standard perf API to access these performance
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counters, driver creates a perf PMU, and related sysfs interfaces in
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/sys/bus/event_source/devices/dfl_fme* to describe available perf events and
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configuration options.
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The "format" directory describes the format of the config field of struct
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perf_event_attr. There are 3 bitfields for config: "evtype" defines which type
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the perf event belongs to; "event" is the identity of the event within its
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category; "portid" is introduced to decide counters set to monitor on FPGA
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overall data or a specific port.
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The "events" directory describes the configuration templates for all available
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events which can be used with perf tool directly. For example, fab_mmio_read
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has the configuration "event=0x06,evtype=0x02,portid=0xff", which shows this
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event belongs to fabric type (0x02), the local event id is 0x06 and it is for
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overall monitoring (portid=0xff).
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Example usage of perf::
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$# perf list |grep dfl_fme
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dfl_fme0/fab_mmio_read/ [Kernel PMU event]
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<...>
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dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event]
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<...>
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$# perf stat -a -e dfl_fme0/fab_mmio_read/ <command>
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or
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$# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0xff/ <command>
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or
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$# perf stat -a -e dfl_fme0/config=0xff2006/ <command>
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Another example, fab_port_mmio_read monitors mmio read of a specific port. So
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its configuration template is "event=0x06,evtype=0x01,portid=?". The portid
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should be explicitly set.
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Its usage of perf::
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$# perf stat -a -e dfl_fme0/fab_port_mmio_read,portid=0x0/ <command>
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or
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$# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0x0/ <command>
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or
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$# perf stat -a -e dfl_fme0/config=0x2006/ <command>
|
|
|
|
Please note for fabric counters, overall perf events (fab_*) and port perf
|
|
events (fab_port_*) actually share one set of counters in hardware, so it can't
|
|
monitor both at the same time. If this set of counters is configured to monitor
|
|
overall data, then per port perf data is not supported. See below example::
|
|
|
|
$# perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,\
|
|
portid=0/ sleep 1
|
|
|
|
Performance counter stats for 'system wide':
|
|
|
|
3 dfl_fme0/fab_mmio_read/
|
|
<not supported> dfl_fme0/fab_port_mmio_write,portid=0x0/
|
|
|
|
1.001750904 seconds time elapsed
|
|
|
|
The driver also provides a "cpumask" sysfs attribute, which contains only one
|
|
CPU id used to access these perf events. Counting on multiple CPU is not allowed
|
|
since they are system-wide counters on FPGA device.
|
|
|
|
The current driver does not support sampling. So "perf record" is unsupported.
|
|
|
|
|
|
Interrupt support
|
|
=================
|
|
Some FME and AFU private features are able to generate interrupts. As mentioned
|
|
above, users could call ioctl (DFL_FPGA_*_GET_IRQ_NUM) to know whether or how
|
|
many interrupts are supported for this private feature. Drivers also implement
|
|
an eventfd based interrupt handling mechanism for users to get notified when
|
|
interrupt happens. Users could set eventfds to driver via
|
|
ioctl (DFL_FPGA_*_SET_IRQ), and then poll/select on these eventfds waiting for
|
|
notification.
|
|
In Current DFL, 3 sub features (Port error, FME global error and AFU interrupt)
|
|
support interrupts.
|
|
|
|
|
|
Add new FIUs support
|
|
====================
|
|
It's possible that developers made some new function blocks (FIUs) under this
|
|
DFL framework, then new platform device driver needs to be developed for the
|
|
new feature dev (FIU) following the same way as existing feature dev drivers
|
|
(e.g. FME and Port/AFU platform device driver). Besides that, it requires
|
|
modification on DFL framework enumeration code too, for new FIU type detection
|
|
and related platform devices creation.
|
|
|
|
|
|
Add new private features support
|
|
================================
|
|
In some cases, we may need to add some new private features to existing FIUs
|
|
(e.g. FME or Port). Developers don't need to touch enumeration code in DFL
|
|
framework, as each private feature will be parsed automatically and related
|
|
mmio resources can be found under FIU platform device created by DFL framework.
|
|
Developer only needs to provide a sub feature driver with matched feature id.
|
|
FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
|
|
could be a reference.
|
|
|
|
Location of DFLs on a PCI Device
|
|
================================
|
|
The original method for finding a DFL on a PCI device assumed the start of the
|
|
first DFL to offset 0 of bar 0. If the first node of the DFL is an FME,
|
|
then further DFLs in the port(s) are specified in FME header registers.
|
|
Alternatively, a PCIe vendor specific capability structure can be used to
|
|
specify the location of all the DFLs on the device, providing flexibility
|
|
for the type of starting node in the DFL. Intel has reserved the
|
|
VSEC ID of 0x43 for this purpose. The vendor specific
|
|
data begins with a 4 byte vendor specific register for the number of DFLs followed 4 byte
|
|
Offset/BIR vendor specific registers for each DFL. Bits 2:0 of Offset/BIR register
|
|
indicates the BAR, and bits 31:3 form the 8 byte aligned offset where bits 2:0 are
|
|
zero.
|
|
::
|
|
|
|
+----------------------------+
|
|
|31 Number of DFLS 0|
|
|
+----------------------------+
|
|
|31 Offset 3|2 BIR 0|
|
|
+----------------------------+
|
|
. . .
|
|
+----------------------------+
|
|
|31 Offset 3|2 BIR 0|
|
|
+----------------------------+
|
|
|
|
Being able to specify more than one DFL per BAR has been considered, but it
|
|
was determined the use case did not provide value. Specifying a single DFL
|
|
per BAR simplifies the implementation and allows for extra error checking.
|
|
|
|
Open discussion
|
|
===============
|
|
FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
|
|
to user now. In the future, if unified user interfaces for reconfiguration are
|
|
added, FME driver should switch to them from ioctl interface.
|