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![Christophe JAILLET](/assets/img/avatar_default.png)
If 'cpufreq_unregister_driver()' fails, just WARN and continue, so that
other resources are freed.
Fixes: de322e0859
("cpufreq: brcmstb-avs-cpufreq: AVS CPUfreq driver for Broadcom STB SoCs")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
[ Viresh: Updated Subject ]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
782 lines
20 KiB
C
782 lines
20 KiB
C
/*
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* CPU frequency scaling for Broadcom SoCs with AVS firmware that
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* supports DVS or DVFS
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*
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* Copyright (c) 2016 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* "AVS" is the name of a firmware developed at Broadcom. It derives
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* its name from the technique called "Adaptive Voltage Scaling".
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* Adaptive voltage scaling was the original purpose of this firmware.
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* The AVS firmware still supports "AVS mode", where all it does is
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* adaptive voltage scaling. However, on some newer Broadcom SoCs, the
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* AVS Firmware, despite its unchanged name, also supports DFS mode and
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* DVFS mode.
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*
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* In the context of this document and the related driver, "AVS" by
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* itself always means the Broadcom firmware and never refers to the
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* technique called "Adaptive Voltage Scaling".
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*
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* The Broadcom STB AVS CPUfreq driver provides voltage and frequency
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* scaling on Broadcom SoCs using AVS firmware with support for DFS and
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* DVFS. The AVS firmware is running on its own co-processor. The
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* driver supports both uniprocessor (UP) and symmetric multiprocessor
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* (SMP) systems which share clock and voltage across all CPUs.
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*
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* Actual voltage and frequency scaling is done solely by the AVS
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* firmware. This driver does not change frequency or voltage itself.
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* It provides a standard CPUfreq interface to the rest of the kernel
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* and to userland. It interfaces with the AVS firmware to effect the
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* requested changes and to report back the current system status in a
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* way that is expected by existing tools.
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*/
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/semaphore.h>
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/* Max number of arguments AVS calls take */
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#define AVS_MAX_CMD_ARGS 4
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/*
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* This macro is used to generate AVS parameter register offsets. For
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* x >= AVS_MAX_CMD_ARGS, it returns 0 to protect against accidental memory
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* access outside of the parameter range. (Offset 0 is the first parameter.)
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*/
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#define AVS_PARAM_MULT(x) ((x) < AVS_MAX_CMD_ARGS ? (x) : 0)
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/* AVS Mailbox Register offsets */
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#define AVS_MBOX_COMMAND 0x00
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#define AVS_MBOX_STATUS 0x04
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#define AVS_MBOX_VOLTAGE0 0x08
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#define AVS_MBOX_TEMP0 0x0c
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#define AVS_MBOX_PV0 0x10
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#define AVS_MBOX_MV0 0x14
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#define AVS_MBOX_PARAM(x) (0x18 + AVS_PARAM_MULT(x) * sizeof(u32))
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#define AVS_MBOX_REVISION 0x28
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#define AVS_MBOX_PSTATE 0x2c
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#define AVS_MBOX_HEARTBEAT 0x30
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#define AVS_MBOX_MAGIC 0x34
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#define AVS_MBOX_SIGMA_HVT 0x38
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#define AVS_MBOX_SIGMA_SVT 0x3c
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#define AVS_MBOX_VOLTAGE1 0x40
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#define AVS_MBOX_TEMP1 0x44
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#define AVS_MBOX_PV1 0x48
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#define AVS_MBOX_MV1 0x4c
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#define AVS_MBOX_FREQUENCY 0x50
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/* AVS Commands */
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#define AVS_CMD_AVAILABLE 0x00
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#define AVS_CMD_DISABLE 0x10
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#define AVS_CMD_ENABLE 0x11
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#define AVS_CMD_S2_ENTER 0x12
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#define AVS_CMD_S2_EXIT 0x13
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#define AVS_CMD_BBM_ENTER 0x14
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#define AVS_CMD_BBM_EXIT 0x15
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#define AVS_CMD_S3_ENTER 0x16
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#define AVS_CMD_S3_EXIT 0x17
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#define AVS_CMD_BALANCE 0x18
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/* PMAP and P-STATE commands */
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#define AVS_CMD_GET_PMAP 0x30
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#define AVS_CMD_SET_PMAP 0x31
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#define AVS_CMD_GET_PSTATE 0x40
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#define AVS_CMD_SET_PSTATE 0x41
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/* Different modes AVS supports (for GET_PMAP/SET_PMAP) */
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#define AVS_MODE_AVS 0x0
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#define AVS_MODE_DFS 0x1
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#define AVS_MODE_DVS 0x2
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#define AVS_MODE_DVFS 0x3
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/*
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* PMAP parameter p1
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* unused:31-24, mdiv_p0:23-16, unused:15-14, pdiv:13-10 , ndiv_int:9-0
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*/
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#define NDIV_INT_SHIFT 0
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#define NDIV_INT_MASK 0x3ff
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#define PDIV_SHIFT 10
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#define PDIV_MASK 0xf
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#define MDIV_P0_SHIFT 16
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#define MDIV_P0_MASK 0xff
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/*
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* PMAP parameter p2
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* mdiv_p4:31-24, mdiv_p3:23-16, mdiv_p2:15:8, mdiv_p1:7:0
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*/
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#define MDIV_P1_SHIFT 0
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#define MDIV_P1_MASK 0xff
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#define MDIV_P2_SHIFT 8
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#define MDIV_P2_MASK 0xff
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#define MDIV_P3_SHIFT 16
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#define MDIV_P3_MASK 0xff
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#define MDIV_P4_SHIFT 24
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#define MDIV_P4_MASK 0xff
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/* Different P-STATES AVS supports (for GET_PSTATE/SET_PSTATE) */
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#define AVS_PSTATE_P0 0x0
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#define AVS_PSTATE_P1 0x1
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#define AVS_PSTATE_P2 0x2
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#define AVS_PSTATE_P3 0x3
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#define AVS_PSTATE_P4 0x4
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#define AVS_PSTATE_MAX AVS_PSTATE_P4
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/* CPU L2 Interrupt Controller Registers */
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#define AVS_CPU_L2_SET0 0x04
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#define AVS_CPU_L2_INT_MASK BIT(31)
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/* AVS Command Status Values */
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#define AVS_STATUS_CLEAR 0x00
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/* Command/notification accepted */
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#define AVS_STATUS_SUCCESS 0xf0
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/* Command/notification rejected */
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#define AVS_STATUS_FAILURE 0xff
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/* Invalid command/notification (unknown) */
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#define AVS_STATUS_INVALID 0xf1
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/* Non-AVS modes are not supported */
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#define AVS_STATUS_NO_SUPP 0xf2
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/* Cannot set P-State until P-Map supplied */
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#define AVS_STATUS_NO_MAP 0xf3
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/* Cannot change P-Map after initial P-Map set */
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#define AVS_STATUS_MAP_SET 0xf4
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/* Max AVS status; higher numbers are used for debugging */
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#define AVS_STATUS_MAX 0xff
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/* Other AVS related constants */
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#define AVS_LOOP_LIMIT 10000
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#define AVS_TIMEOUT 300 /* in ms; expected completion is < 10ms */
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#define AVS_FIRMWARE_MAGIC 0xa11600d1
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#define BRCM_AVS_CPUFREQ_PREFIX "brcmstb-avs"
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#define BRCM_AVS_CPUFREQ_NAME BRCM_AVS_CPUFREQ_PREFIX "-cpufreq"
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#define BRCM_AVS_CPU_DATA "brcm,avs-cpu-data-mem"
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#define BRCM_AVS_CPU_INTR "brcm,avs-cpu-l2-intr"
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#define BRCM_AVS_HOST_INTR "sw_intr"
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struct pmap {
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unsigned int mode;
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unsigned int p1;
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unsigned int p2;
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unsigned int state;
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};
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struct private_data {
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void __iomem *base;
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void __iomem *avs_intr_base;
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struct device *dev;
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struct completion done;
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struct semaphore sem;
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struct pmap pmap;
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int host_irq;
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};
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static void __iomem *__map_region(const char *name)
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{
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struct device_node *np;
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void __iomem *ptr;
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np = of_find_compatible_node(NULL, NULL, name);
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if (!np)
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return NULL;
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ptr = of_iomap(np, 0);
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of_node_put(np);
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return ptr;
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}
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static unsigned long wait_for_avs_command(struct private_data *priv,
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unsigned long timeout)
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{
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unsigned long time_left = 0;
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u32 val;
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/* Event driven, wait for the command interrupt */
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if (priv->host_irq >= 0)
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return wait_for_completion_timeout(&priv->done,
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msecs_to_jiffies(timeout));
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/* Polling for command completion */
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do {
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time_left = timeout;
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val = readl(priv->base + AVS_MBOX_STATUS);
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if (val)
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break;
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usleep_range(1000, 2000);
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} while (--timeout);
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return time_left;
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}
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static int __issue_avs_command(struct private_data *priv, unsigned int cmd,
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unsigned int num_in, unsigned int num_out,
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u32 args[])
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{
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void __iomem *base = priv->base;
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unsigned long time_left;
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unsigned int i;
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int ret;
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u32 val;
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ret = down_interruptible(&priv->sem);
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if (ret)
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return ret;
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/*
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* Make sure no other command is currently running: cmd is 0 if AVS
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* co-processor is idle. Due to the guard above, we should almost never
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* have to wait here.
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*/
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for (i = 0, val = 1; val != 0 && i < AVS_LOOP_LIMIT; i++)
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val = readl(base + AVS_MBOX_COMMAND);
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/* Give the caller a chance to retry if AVS is busy. */
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if (i == AVS_LOOP_LIMIT) {
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ret = -EAGAIN;
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goto out;
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}
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/* Clear status before we begin. */
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writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS);
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/* Provide input parameters */
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for (i = 0; i < num_in; i++)
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writel(args[i], base + AVS_MBOX_PARAM(i));
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/* Protect from spurious interrupts. */
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reinit_completion(&priv->done);
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/* Now issue the command & tell firmware to wake up to process it. */
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writel(cmd, base + AVS_MBOX_COMMAND);
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writel(AVS_CPU_L2_INT_MASK, priv->avs_intr_base + AVS_CPU_L2_SET0);
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/* Wait for AVS co-processor to finish processing the command. */
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time_left = wait_for_avs_command(priv, AVS_TIMEOUT);
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/*
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* If the AVS status is not in the expected range, it means AVS didn't
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* complete our command in time, and we return an error. Also, if there
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* is no "time left", we timed out waiting for the interrupt.
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*/
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val = readl(base + AVS_MBOX_STATUS);
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if (time_left == 0 || val == 0 || val > AVS_STATUS_MAX) {
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dev_err(priv->dev, "AVS command %#x didn't complete in time\n",
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cmd);
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dev_err(priv->dev, " Time left: %u ms, AVS status: %#x\n",
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jiffies_to_msecs(time_left), val);
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ret = -ETIMEDOUT;
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goto out;
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}
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/* Process returned values */
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for (i = 0; i < num_out; i++)
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args[i] = readl(base + AVS_MBOX_PARAM(i));
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/* Clear status to tell AVS co-processor we are done. */
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writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS);
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/* Convert firmware errors to errno's as much as possible. */
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switch (val) {
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case AVS_STATUS_INVALID:
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ret = -EINVAL;
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break;
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case AVS_STATUS_NO_SUPP:
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ret = -ENOTSUPP;
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break;
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case AVS_STATUS_NO_MAP:
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ret = -ENOENT;
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break;
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case AVS_STATUS_MAP_SET:
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ret = -EEXIST;
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break;
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case AVS_STATUS_FAILURE:
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ret = -EIO;
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break;
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}
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out:
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up(&priv->sem);
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return ret;
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}
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static irqreturn_t irq_handler(int irq, void *data)
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{
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struct private_data *priv = data;
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/* AVS command completed execution. Wake up __issue_avs_command(). */
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complete(&priv->done);
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return IRQ_HANDLED;
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}
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static char *brcm_avs_mode_to_string(unsigned int mode)
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{
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switch (mode) {
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case AVS_MODE_AVS:
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return "AVS";
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case AVS_MODE_DFS:
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return "DFS";
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case AVS_MODE_DVS:
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return "DVS";
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case AVS_MODE_DVFS:
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return "DVFS";
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}
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return NULL;
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}
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static void brcm_avs_parse_p1(u32 p1, unsigned int *mdiv_p0, unsigned int *pdiv,
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unsigned int *ndiv)
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{
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*mdiv_p0 = (p1 >> MDIV_P0_SHIFT) & MDIV_P0_MASK;
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*pdiv = (p1 >> PDIV_SHIFT) & PDIV_MASK;
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*ndiv = (p1 >> NDIV_INT_SHIFT) & NDIV_INT_MASK;
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}
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static void brcm_avs_parse_p2(u32 p2, unsigned int *mdiv_p1,
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unsigned int *mdiv_p2, unsigned int *mdiv_p3,
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unsigned int *mdiv_p4)
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{
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*mdiv_p4 = (p2 >> MDIV_P4_SHIFT) & MDIV_P4_MASK;
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*mdiv_p3 = (p2 >> MDIV_P3_SHIFT) & MDIV_P3_MASK;
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*mdiv_p2 = (p2 >> MDIV_P2_SHIFT) & MDIV_P2_MASK;
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*mdiv_p1 = (p2 >> MDIV_P1_SHIFT) & MDIV_P1_MASK;
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}
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static int brcm_avs_get_pmap(struct private_data *priv, struct pmap *pmap)
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{
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u32 args[AVS_MAX_CMD_ARGS];
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int ret;
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ret = __issue_avs_command(priv, AVS_CMD_GET_PMAP, 0, 4, args);
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if (ret || !pmap)
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return ret;
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pmap->mode = args[0];
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pmap->p1 = args[1];
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pmap->p2 = args[2];
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pmap->state = args[3];
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return 0;
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}
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static int brcm_avs_set_pmap(struct private_data *priv, struct pmap *pmap)
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{
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u32 args[AVS_MAX_CMD_ARGS];
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args[0] = pmap->mode;
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args[1] = pmap->p1;
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args[2] = pmap->p2;
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args[3] = pmap->state;
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return __issue_avs_command(priv, AVS_CMD_SET_PMAP, 4, 0, args);
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}
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static int brcm_avs_get_pstate(struct private_data *priv, unsigned int *pstate)
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{
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u32 args[AVS_MAX_CMD_ARGS];
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int ret;
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ret = __issue_avs_command(priv, AVS_CMD_GET_PSTATE, 0, 1, args);
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if (ret)
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return ret;
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*pstate = args[0];
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return 0;
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}
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static int brcm_avs_set_pstate(struct private_data *priv, unsigned int pstate)
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{
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u32 args[AVS_MAX_CMD_ARGS];
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args[0] = pstate;
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return __issue_avs_command(priv, AVS_CMD_SET_PSTATE, 1, 0, args);
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}
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static u32 brcm_avs_get_voltage(void __iomem *base)
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{
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return readl(base + AVS_MBOX_VOLTAGE1);
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}
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static u32 brcm_avs_get_frequency(void __iomem *base)
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{
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return readl(base + AVS_MBOX_FREQUENCY) * 1000; /* in kHz */
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}
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/*
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* We determine which frequencies are supported by cycling through all P-states
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* and reading back what frequency we are running at for each P-state.
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*/
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static struct cpufreq_frequency_table *
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brcm_avs_get_freq_table(struct device *dev, struct private_data *priv)
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{
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struct cpufreq_frequency_table *table;
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unsigned int pstate;
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int i, ret;
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/* Remember P-state for later */
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ret = brcm_avs_get_pstate(priv, &pstate);
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if (ret)
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return ERR_PTR(ret);
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table = devm_kcalloc(dev, AVS_PSTATE_MAX + 1, sizeof(*table),
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GFP_KERNEL);
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if (!table)
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return ERR_PTR(-ENOMEM);
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for (i = AVS_PSTATE_P0; i <= AVS_PSTATE_MAX; i++) {
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ret = brcm_avs_set_pstate(priv, i);
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if (ret)
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return ERR_PTR(ret);
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table[i].frequency = brcm_avs_get_frequency(priv->base);
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table[i].driver_data = i;
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}
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table[i].frequency = CPUFREQ_TABLE_END;
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/* Restore P-state */
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ret = brcm_avs_set_pstate(priv, pstate);
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if (ret)
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return ERR_PTR(ret);
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return table;
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}
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/*
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* To ensure the right firmware is running we need to
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* - check the MAGIC matches what we expect
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* - brcm_avs_get_pmap() doesn't return -ENOTSUPP or -EINVAL
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* We need to set up our interrupt handling before calling brcm_avs_get_pmap()!
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*/
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static bool brcm_avs_is_firmware_loaded(struct private_data *priv)
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{
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u32 magic;
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int rc;
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rc = brcm_avs_get_pmap(priv, NULL);
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magic = readl(priv->base + AVS_MBOX_MAGIC);
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|
return (magic == AVS_FIRMWARE_MAGIC) && ((rc != -ENOTSUPP) ||
|
|
(rc != -EINVAL));
|
|
}
|
|
|
|
static unsigned int brcm_avs_cpufreq_get(unsigned int cpu)
|
|
{
|
|
struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
|
|
struct private_data *priv = policy->driver_data;
|
|
|
|
cpufreq_cpu_put(policy);
|
|
|
|
return brcm_avs_get_frequency(priv->base);
|
|
}
|
|
|
|
static int brcm_avs_target_index(struct cpufreq_policy *policy,
|
|
unsigned int index)
|
|
{
|
|
return brcm_avs_set_pstate(policy->driver_data,
|
|
policy->freq_table[index].driver_data);
|
|
}
|
|
|
|
static int brcm_avs_suspend(struct cpufreq_policy *policy)
|
|
{
|
|
struct private_data *priv = policy->driver_data;
|
|
int ret;
|
|
|
|
ret = brcm_avs_get_pmap(priv, &priv->pmap);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* We can't use the P-state returned by brcm_avs_get_pmap(), since
|
|
* that's the initial P-state from when the P-map was downloaded to the
|
|
* AVS co-processor, not necessarily the P-state we are running at now.
|
|
* So, we get the current P-state explicitly.
|
|
*/
|
|
ret = brcm_avs_get_pstate(priv, &priv->pmap.state);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* This is best effort. Nothing to do if it fails. */
|
|
(void)__issue_avs_command(priv, AVS_CMD_S2_ENTER, 0, 0, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int brcm_avs_resume(struct cpufreq_policy *policy)
|
|
{
|
|
struct private_data *priv = policy->driver_data;
|
|
int ret;
|
|
|
|
/* This is best effort. Nothing to do if it fails. */
|
|
(void)__issue_avs_command(priv, AVS_CMD_S2_EXIT, 0, 0, NULL);
|
|
|
|
ret = brcm_avs_set_pmap(priv, &priv->pmap);
|
|
if (ret == -EEXIST) {
|
|
struct platform_device *pdev = cpufreq_get_driver_data();
|
|
struct device *dev = &pdev->dev;
|
|
|
|
dev_warn(dev, "PMAP was already set\n");
|
|
ret = 0;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* All initialization code that we only want to execute once goes here. Setup
|
|
* code that can be re-tried on every core (if it failed before) can go into
|
|
* brcm_avs_cpufreq_init().
|
|
*/
|
|
static int brcm_avs_prepare_init(struct platform_device *pdev)
|
|
{
|
|
struct private_data *priv;
|
|
struct device *dev;
|
|
int ret;
|
|
|
|
dev = &pdev->dev;
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->dev = dev;
|
|
sema_init(&priv->sem, 1);
|
|
init_completion(&priv->done);
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
priv->base = __map_region(BRCM_AVS_CPU_DATA);
|
|
if (!priv->base) {
|
|
dev_err(dev, "Couldn't find property %s in device tree.\n",
|
|
BRCM_AVS_CPU_DATA);
|
|
return -ENOENT;
|
|
}
|
|
|
|
priv->avs_intr_base = __map_region(BRCM_AVS_CPU_INTR);
|
|
if (!priv->avs_intr_base) {
|
|
dev_err(dev, "Couldn't find property %s in device tree.\n",
|
|
BRCM_AVS_CPU_INTR);
|
|
ret = -ENOENT;
|
|
goto unmap_base;
|
|
}
|
|
|
|
priv->host_irq = platform_get_irq_byname(pdev, BRCM_AVS_HOST_INTR);
|
|
|
|
ret = devm_request_irq(dev, priv->host_irq, irq_handler,
|
|
IRQF_TRIGGER_RISING,
|
|
BRCM_AVS_HOST_INTR, priv);
|
|
if (ret && priv->host_irq >= 0) {
|
|
dev_err(dev, "IRQ request failed: %s (%d) -- %d\n",
|
|
BRCM_AVS_HOST_INTR, priv->host_irq, ret);
|
|
goto unmap_intr_base;
|
|
}
|
|
|
|
if (brcm_avs_is_firmware_loaded(priv))
|
|
return 0;
|
|
|
|
dev_err(dev, "AVS firmware is not loaded or doesn't support DVFS\n");
|
|
ret = -ENODEV;
|
|
|
|
unmap_intr_base:
|
|
iounmap(priv->avs_intr_base);
|
|
unmap_base:
|
|
iounmap(priv->base);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void brcm_avs_prepare_uninit(struct platform_device *pdev)
|
|
{
|
|
struct private_data *priv;
|
|
|
|
priv = platform_get_drvdata(pdev);
|
|
|
|
iounmap(priv->avs_intr_base);
|
|
iounmap(priv->base);
|
|
}
|
|
|
|
static int brcm_avs_cpufreq_init(struct cpufreq_policy *policy)
|
|
{
|
|
struct cpufreq_frequency_table *freq_table;
|
|
struct platform_device *pdev;
|
|
struct private_data *priv;
|
|
struct device *dev;
|
|
int ret;
|
|
|
|
pdev = cpufreq_get_driver_data();
|
|
priv = platform_get_drvdata(pdev);
|
|
policy->driver_data = priv;
|
|
dev = &pdev->dev;
|
|
|
|
freq_table = brcm_avs_get_freq_table(dev, priv);
|
|
if (IS_ERR(freq_table)) {
|
|
ret = PTR_ERR(freq_table);
|
|
dev_err(dev, "Couldn't determine frequency table (%d).\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
policy->freq_table = freq_table;
|
|
|
|
/* All cores share the same clock and thus the same policy. */
|
|
cpumask_setall(policy->cpus);
|
|
|
|
ret = __issue_avs_command(priv, AVS_CMD_ENABLE, 0, 0, NULL);
|
|
if (!ret) {
|
|
unsigned int pstate;
|
|
|
|
ret = brcm_avs_get_pstate(priv, &pstate);
|
|
if (!ret) {
|
|
policy->cur = freq_table[pstate].frequency;
|
|
dev_info(dev, "registered\n");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
dev_err(dev, "couldn't initialize driver (%d)\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t show_brcm_avs_pstate(struct cpufreq_policy *policy, char *buf)
|
|
{
|
|
struct private_data *priv = policy->driver_data;
|
|
unsigned int pstate;
|
|
|
|
if (brcm_avs_get_pstate(priv, &pstate))
|
|
return sprintf(buf, "<unknown>\n");
|
|
|
|
return sprintf(buf, "%u\n", pstate);
|
|
}
|
|
|
|
static ssize_t show_brcm_avs_mode(struct cpufreq_policy *policy, char *buf)
|
|
{
|
|
struct private_data *priv = policy->driver_data;
|
|
struct pmap pmap;
|
|
|
|
if (brcm_avs_get_pmap(priv, &pmap))
|
|
return sprintf(buf, "<unknown>\n");
|
|
|
|
return sprintf(buf, "%s %u\n", brcm_avs_mode_to_string(pmap.mode),
|
|
pmap.mode);
|
|
}
|
|
|
|
static ssize_t show_brcm_avs_pmap(struct cpufreq_policy *policy, char *buf)
|
|
{
|
|
unsigned int mdiv_p0, mdiv_p1, mdiv_p2, mdiv_p3, mdiv_p4;
|
|
struct private_data *priv = policy->driver_data;
|
|
unsigned int ndiv, pdiv;
|
|
struct pmap pmap;
|
|
|
|
if (brcm_avs_get_pmap(priv, &pmap))
|
|
return sprintf(buf, "<unknown>\n");
|
|
|
|
brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv);
|
|
brcm_avs_parse_p2(pmap.p2, &mdiv_p1, &mdiv_p2, &mdiv_p3, &mdiv_p4);
|
|
|
|
return sprintf(buf, "0x%08x 0x%08x %u %u %u %u %u %u %u %u %u\n",
|
|
pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2,
|
|
mdiv_p3, mdiv_p4, pmap.mode, pmap.state);
|
|
}
|
|
|
|
static ssize_t show_brcm_avs_voltage(struct cpufreq_policy *policy, char *buf)
|
|
{
|
|
struct private_data *priv = policy->driver_data;
|
|
|
|
return sprintf(buf, "0x%08x\n", brcm_avs_get_voltage(priv->base));
|
|
}
|
|
|
|
static ssize_t show_brcm_avs_frequency(struct cpufreq_policy *policy, char *buf)
|
|
{
|
|
struct private_data *priv = policy->driver_data;
|
|
|
|
return sprintf(buf, "0x%08x\n", brcm_avs_get_frequency(priv->base));
|
|
}
|
|
|
|
cpufreq_freq_attr_ro(brcm_avs_pstate);
|
|
cpufreq_freq_attr_ro(brcm_avs_mode);
|
|
cpufreq_freq_attr_ro(brcm_avs_pmap);
|
|
cpufreq_freq_attr_ro(brcm_avs_voltage);
|
|
cpufreq_freq_attr_ro(brcm_avs_frequency);
|
|
|
|
static struct freq_attr *brcm_avs_cpufreq_attr[] = {
|
|
&cpufreq_freq_attr_scaling_available_freqs,
|
|
&brcm_avs_pstate,
|
|
&brcm_avs_mode,
|
|
&brcm_avs_pmap,
|
|
&brcm_avs_voltage,
|
|
&brcm_avs_frequency,
|
|
NULL
|
|
};
|
|
|
|
static struct cpufreq_driver brcm_avs_driver = {
|
|
.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
|
|
.verify = cpufreq_generic_frequency_table_verify,
|
|
.target_index = brcm_avs_target_index,
|
|
.get = brcm_avs_cpufreq_get,
|
|
.suspend = brcm_avs_suspend,
|
|
.resume = brcm_avs_resume,
|
|
.init = brcm_avs_cpufreq_init,
|
|
.attr = brcm_avs_cpufreq_attr,
|
|
.name = BRCM_AVS_CPUFREQ_PREFIX,
|
|
};
|
|
|
|
static int brcm_avs_cpufreq_probe(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
|
|
ret = brcm_avs_prepare_init(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
brcm_avs_driver.driver_data = pdev;
|
|
|
|
ret = cpufreq_register_driver(&brcm_avs_driver);
|
|
if (ret)
|
|
brcm_avs_prepare_uninit(pdev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int brcm_avs_cpufreq_remove(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
|
|
ret = cpufreq_unregister_driver(&brcm_avs_driver);
|
|
WARN_ON(ret);
|
|
|
|
brcm_avs_prepare_uninit(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id brcm_avs_cpufreq_match[] = {
|
|
{ .compatible = BRCM_AVS_CPU_DATA },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, brcm_avs_cpufreq_match);
|
|
|
|
static struct platform_driver brcm_avs_cpufreq_platdrv = {
|
|
.driver = {
|
|
.name = BRCM_AVS_CPUFREQ_NAME,
|
|
.of_match_table = brcm_avs_cpufreq_match,
|
|
},
|
|
.probe = brcm_avs_cpufreq_probe,
|
|
.remove = brcm_avs_cpufreq_remove,
|
|
};
|
|
module_platform_driver(brcm_avs_cpufreq_platdrv);
|
|
|
|
MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
|
|
MODULE_DESCRIPTION("CPUfreq driver for Broadcom STB AVS");
|
|
MODULE_LICENSE("GPL");
|