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Provide enough functionality to utilize the mailbox of a memory device. The mailbox is used to interact with the firmware running on the memory device. The flow is proven with one implemented command, "identify". Because the class code has already told the driver this is a memory device and the identify command is mandatory. CXL devices contain an array of capabilities that describe the interactions software can have with the device or firmware running on the device. A CXL compliant device must implement the device status and the mailbox capability. Additionally, a CXL compliant memory device must implement the memory device capability. Each of the capabilities can [will] provide an offset within the MMIO region for interacting with the CXL device. The capabilities tell the driver how to find and map the register space for CXL Memory Devices. The registers are required to utilize the CXL spec defined mailbox interface. The spec outlines two mailboxes, primary and secondary. The secondary mailbox is earmarked for system firmware, and not handled in this driver. Primary mailboxes are capable of generating an interrupt when submitting a background command. That implementation is saved for a later time. Reported-by: Colin Ian King <colin.king@canonical.com> (coverity) Reported-by: Dan Carpenter <dan.carpenter@oracle.com> (smatch) Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> (v2) Link: https://www.computeexpresslink.org/download-the-specification Link: https://lore.kernel.org/r/20210217040958.1354670-3-ben.widawsky@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
31 lines
854 B
C
31 lines
854 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#ifndef __CXL_PCI_H__
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#define __CXL_PCI_H__
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#define CXL_MEMORY_PROGIF 0x10
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/*
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* See section 8.1 Configuration Space Registers in the CXL 2.0
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* Specification
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*/
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#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
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#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
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#define PCI_DVSEC_ID_CXL 0x0
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#define PCI_DVSEC_ID_CXL_REGLOC_OFFSET 0x8
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#define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC
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/* BAR Indicator Register (BIR) */
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#define CXL_REGLOC_BIR_MASK GENMASK(2, 0)
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/* Register Block Identifier (RBI) */
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#define CXL_REGLOC_RBI_MASK GENMASK(15, 8)
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#define CXL_REGLOC_RBI_EMPTY 0
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#define CXL_REGLOC_RBI_COMPONENT 1
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#define CXL_REGLOC_RBI_VIRT 2
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#define CXL_REGLOC_RBI_MEMDEV 3
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#define CXL_REGLOC_ADDR_MASK GENMASK(31, 16)
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#endif /* __CXL_PCI_H__ */
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