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![Barry Song](/assets/img/avatar_default.png)
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20201027215252.25820-8-song.bao.hua@hisilicon.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
607 lines
15 KiB
C
607 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2019 HiSilicon Limited. */
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#include <linux/bitfield.h>
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include "virt-dma.h"
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#define HISI_DMA_SQ_BASE_L 0x0
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#define HISI_DMA_SQ_BASE_H 0x4
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#define HISI_DMA_SQ_DEPTH 0x8
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#define HISI_DMA_SQ_TAIL_PTR 0xc
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#define HISI_DMA_CQ_BASE_L 0x10
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#define HISI_DMA_CQ_BASE_H 0x14
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#define HISI_DMA_CQ_DEPTH 0x18
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#define HISI_DMA_CQ_HEAD_PTR 0x1c
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#define HISI_DMA_CTRL0 0x20
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#define HISI_DMA_CTRL0_QUEUE_EN_S 0
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#define HISI_DMA_CTRL0_QUEUE_PAUSE_S 4
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#define HISI_DMA_CTRL1 0x24
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#define HISI_DMA_CTRL1_QUEUE_RESET_S 0
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#define HISI_DMA_Q_FSM_STS 0x30
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#define HISI_DMA_FSM_STS_MASK GENMASK(3, 0)
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#define HISI_DMA_INT_STS 0x40
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#define HISI_DMA_INT_STS_MASK GENMASK(12, 0)
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#define HISI_DMA_INT_MSK 0x44
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#define HISI_DMA_MODE 0x217c
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#define HISI_DMA_OFFSET 0x100
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#define HISI_DMA_MSI_NUM 30
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#define HISI_DMA_CHAN_NUM 30
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#define HISI_DMA_Q_DEPTH_VAL 1024
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#define PCI_BAR_2 2
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enum hisi_dma_mode {
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EP = 0,
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RC,
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};
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enum hisi_dma_chan_status {
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DISABLE = -1,
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IDLE = 0,
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RUN,
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CPL,
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PAUSE,
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HALT,
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ABORT,
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WAIT,
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BUFFCLR,
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};
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struct hisi_dma_sqe {
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__le32 dw0;
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#define OPCODE_MASK GENMASK(3, 0)
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#define OPCODE_SMALL_PACKAGE 0x1
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#define OPCODE_M2M 0x4
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#define LOCAL_IRQ_EN BIT(8)
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#define ATTR_SRC_MASK GENMASK(14, 12)
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__le32 dw1;
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__le32 dw2;
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#define ATTR_DST_MASK GENMASK(26, 24)
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__le32 length;
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__le64 src_addr;
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__le64 dst_addr;
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};
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struct hisi_dma_cqe {
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__le32 rsv0;
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__le32 rsv1;
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__le16 sq_head;
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__le16 rsv2;
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__le16 rsv3;
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__le16 w0;
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#define STATUS_MASK GENMASK(15, 1)
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#define STATUS_SUCC 0x0
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#define VALID_BIT BIT(0)
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};
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struct hisi_dma_desc {
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struct virt_dma_desc vd;
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struct hisi_dma_sqe sqe;
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};
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struct hisi_dma_chan {
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struct virt_dma_chan vc;
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struct hisi_dma_dev *hdma_dev;
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struct hisi_dma_sqe *sq;
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struct hisi_dma_cqe *cq;
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dma_addr_t sq_dma;
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dma_addr_t cq_dma;
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u32 sq_tail;
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u32 cq_head;
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u32 qp_num;
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enum hisi_dma_chan_status status;
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struct hisi_dma_desc *desc;
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};
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struct hisi_dma_dev {
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struct pci_dev *pdev;
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void __iomem *base;
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struct dma_device dma_dev;
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u32 chan_num;
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u32 chan_depth;
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struct hisi_dma_chan chan[];
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};
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static inline struct hisi_dma_chan *to_hisi_dma_chan(struct dma_chan *c)
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{
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return container_of(c, struct hisi_dma_chan, vc.chan);
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}
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static inline struct hisi_dma_desc *to_hisi_dma_desc(struct virt_dma_desc *vd)
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{
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return container_of(vd, struct hisi_dma_desc, vd);
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}
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static inline void hisi_dma_chan_write(void __iomem *base, u32 reg, u32 index,
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u32 val)
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{
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writel_relaxed(val, base + reg + index * HISI_DMA_OFFSET);
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}
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static inline void hisi_dma_update_bit(void __iomem *addr, u32 pos, bool val)
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{
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u32 tmp;
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tmp = readl_relaxed(addr);
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tmp = val ? tmp | BIT(pos) : tmp & ~BIT(pos);
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writel_relaxed(tmp, addr);
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}
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static void hisi_dma_free_irq_vectors(void *data)
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{
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pci_free_irq_vectors(data);
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}
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static void hisi_dma_pause_dma(struct hisi_dma_dev *hdma_dev, u32 index,
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bool pause)
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{
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void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
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HISI_DMA_OFFSET;
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hisi_dma_update_bit(addr, HISI_DMA_CTRL0_QUEUE_PAUSE_S, pause);
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}
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static void hisi_dma_enable_dma(struct hisi_dma_dev *hdma_dev, u32 index,
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bool enable)
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{
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void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
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HISI_DMA_OFFSET;
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hisi_dma_update_bit(addr, HISI_DMA_CTRL0_QUEUE_EN_S, enable);
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}
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static void hisi_dma_mask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index)
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{
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hisi_dma_chan_write(hdma_dev->base, HISI_DMA_INT_MSK, qp_index,
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HISI_DMA_INT_STS_MASK);
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}
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static void hisi_dma_unmask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index)
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{
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void __iomem *base = hdma_dev->base;
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hisi_dma_chan_write(base, HISI_DMA_INT_STS, qp_index,
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HISI_DMA_INT_STS_MASK);
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hisi_dma_chan_write(base, HISI_DMA_INT_MSK, qp_index, 0);
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}
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static void hisi_dma_do_reset(struct hisi_dma_dev *hdma_dev, u32 index)
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{
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void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL1 + index *
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HISI_DMA_OFFSET;
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hisi_dma_update_bit(addr, HISI_DMA_CTRL1_QUEUE_RESET_S, 1);
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}
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static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index)
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{
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hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, index, 0);
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hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR, index, 0);
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}
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static void hisi_dma_reset_hw_chan(struct hisi_dma_chan *chan)
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{
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struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
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u32 index = chan->qp_num, tmp;
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int ret;
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hisi_dma_pause_dma(hdma_dev, index, true);
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hisi_dma_enable_dma(hdma_dev, index, false);
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hisi_dma_mask_irq(hdma_dev, index);
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ret = readl_relaxed_poll_timeout(hdma_dev->base +
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HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp,
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FIELD_GET(HISI_DMA_FSM_STS_MASK, tmp) != RUN, 10, 1000);
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if (ret) {
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dev_err(&hdma_dev->pdev->dev, "disable channel timeout!\n");
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WARN_ON(1);
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}
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hisi_dma_do_reset(hdma_dev, index);
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hisi_dma_reset_qp_point(hdma_dev, index);
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hisi_dma_pause_dma(hdma_dev, index, false);
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hisi_dma_enable_dma(hdma_dev, index, true);
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hisi_dma_unmask_irq(hdma_dev, index);
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ret = readl_relaxed_poll_timeout(hdma_dev->base +
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HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp,
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FIELD_GET(HISI_DMA_FSM_STS_MASK, tmp) == IDLE, 10, 1000);
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if (ret) {
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dev_err(&hdma_dev->pdev->dev, "reset channel timeout!\n");
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WARN_ON(1);
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}
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}
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static void hisi_dma_free_chan_resources(struct dma_chan *c)
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{
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struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
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struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
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hisi_dma_reset_hw_chan(chan);
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vchan_free_chan_resources(&chan->vc);
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memset(chan->sq, 0, sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth);
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memset(chan->cq, 0, sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth);
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chan->sq_tail = 0;
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chan->cq_head = 0;
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chan->status = DISABLE;
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}
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static void hisi_dma_desc_free(struct virt_dma_desc *vd)
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{
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kfree(to_hisi_dma_desc(vd));
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}
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static struct dma_async_tx_descriptor *
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hisi_dma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dst, dma_addr_t src,
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size_t len, unsigned long flags)
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{
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struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
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struct hisi_dma_desc *desc;
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desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
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if (!desc)
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return NULL;
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desc->sqe.length = cpu_to_le32(len);
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desc->sqe.src_addr = cpu_to_le64(src);
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desc->sqe.dst_addr = cpu_to_le64(dst);
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return vchan_tx_prep(&chan->vc, &desc->vd, flags);
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}
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static enum dma_status
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hisi_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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{
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return dma_cookie_status(c, cookie, txstate);
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}
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static void hisi_dma_start_transfer(struct hisi_dma_chan *chan)
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{
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struct hisi_dma_sqe *sqe = chan->sq + chan->sq_tail;
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struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
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struct hisi_dma_desc *desc;
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struct virt_dma_desc *vd;
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vd = vchan_next_desc(&chan->vc);
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if (!vd) {
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dev_err(&hdma_dev->pdev->dev, "no issued task!\n");
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chan->desc = NULL;
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return;
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}
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list_del(&vd->node);
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desc = to_hisi_dma_desc(vd);
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chan->desc = desc;
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memcpy(sqe, &desc->sqe, sizeof(struct hisi_dma_sqe));
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/* update other field in sqe */
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sqe->dw0 = cpu_to_le32(FIELD_PREP(OPCODE_MASK, OPCODE_M2M));
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sqe->dw0 |= cpu_to_le32(LOCAL_IRQ_EN);
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/* make sure data has been updated in sqe */
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wmb();
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/* update sq tail, point to new sqe position */
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chan->sq_tail = (chan->sq_tail + 1) % hdma_dev->chan_depth;
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/* update sq_tail to trigger a new task */
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hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, chan->qp_num,
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chan->sq_tail);
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}
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static void hisi_dma_issue_pending(struct dma_chan *c)
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{
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struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
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unsigned long flags;
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spin_lock_irqsave(&chan->vc.lock, flags);
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if (vchan_issue_pending(&chan->vc))
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hisi_dma_start_transfer(chan);
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spin_unlock_irqrestore(&chan->vc.lock, flags);
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}
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static int hisi_dma_terminate_all(struct dma_chan *c)
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{
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struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
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unsigned long flags;
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LIST_HEAD(head);
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spin_lock_irqsave(&chan->vc.lock, flags);
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hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, true);
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if (chan->desc) {
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vchan_terminate_vdesc(&chan->desc->vd);
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chan->desc = NULL;
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}
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vchan_get_all_descriptors(&chan->vc, &head);
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spin_unlock_irqrestore(&chan->vc.lock, flags);
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vchan_dma_desc_free_list(&chan->vc, &head);
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hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, false);
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return 0;
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}
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static void hisi_dma_synchronize(struct dma_chan *c)
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{
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struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
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vchan_synchronize(&chan->vc);
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}
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static int hisi_dma_alloc_qps_mem(struct hisi_dma_dev *hdma_dev)
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{
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size_t sq_size = sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth;
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size_t cq_size = sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth;
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struct device *dev = &hdma_dev->pdev->dev;
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struct hisi_dma_chan *chan;
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int i;
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for (i = 0; i < hdma_dev->chan_num; i++) {
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chan = &hdma_dev->chan[i];
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chan->sq = dmam_alloc_coherent(dev, sq_size, &chan->sq_dma,
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GFP_KERNEL);
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if (!chan->sq)
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return -ENOMEM;
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chan->cq = dmam_alloc_coherent(dev, cq_size, &chan->cq_dma,
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GFP_KERNEL);
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if (!chan->cq)
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return -ENOMEM;
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}
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return 0;
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}
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static void hisi_dma_init_hw_qp(struct hisi_dma_dev *hdma_dev, u32 index)
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{
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struct hisi_dma_chan *chan = &hdma_dev->chan[index];
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u32 hw_depth = hdma_dev->chan_depth - 1;
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void __iomem *base = hdma_dev->base;
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/* set sq, cq base */
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hisi_dma_chan_write(base, HISI_DMA_SQ_BASE_L, index,
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lower_32_bits(chan->sq_dma));
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hisi_dma_chan_write(base, HISI_DMA_SQ_BASE_H, index,
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upper_32_bits(chan->sq_dma));
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hisi_dma_chan_write(base, HISI_DMA_CQ_BASE_L, index,
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lower_32_bits(chan->cq_dma));
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hisi_dma_chan_write(base, HISI_DMA_CQ_BASE_H, index,
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upper_32_bits(chan->cq_dma));
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/* set sq, cq depth */
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hisi_dma_chan_write(base, HISI_DMA_SQ_DEPTH, index, hw_depth);
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hisi_dma_chan_write(base, HISI_DMA_CQ_DEPTH, index, hw_depth);
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/* init sq tail and cq head */
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hisi_dma_chan_write(base, HISI_DMA_SQ_TAIL_PTR, index, 0);
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hisi_dma_chan_write(base, HISI_DMA_CQ_HEAD_PTR, index, 0);
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}
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static void hisi_dma_enable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
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{
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hisi_dma_init_hw_qp(hdma_dev, qp_index);
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hisi_dma_unmask_irq(hdma_dev, qp_index);
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hisi_dma_enable_dma(hdma_dev, qp_index, true);
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}
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static void hisi_dma_disable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
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{
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hisi_dma_reset_hw_chan(&hdma_dev->chan[qp_index]);
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}
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static void hisi_dma_enable_qps(struct hisi_dma_dev *hdma_dev)
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{
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int i;
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for (i = 0; i < hdma_dev->chan_num; i++) {
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hdma_dev->chan[i].qp_num = i;
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hdma_dev->chan[i].hdma_dev = hdma_dev;
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hdma_dev->chan[i].vc.desc_free = hisi_dma_desc_free;
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vchan_init(&hdma_dev->chan[i].vc, &hdma_dev->dma_dev);
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hisi_dma_enable_qp(hdma_dev, i);
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}
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}
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static void hisi_dma_disable_qps(struct hisi_dma_dev *hdma_dev)
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{
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int i;
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for (i = 0; i < hdma_dev->chan_num; i++) {
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hisi_dma_disable_qp(hdma_dev, i);
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tasklet_kill(&hdma_dev->chan[i].vc.task);
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}
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}
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static irqreturn_t hisi_dma_irq(int irq, void *data)
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{
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struct hisi_dma_chan *chan = data;
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struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
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struct hisi_dma_desc *desc;
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struct hisi_dma_cqe *cqe;
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spin_lock(&chan->vc.lock);
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desc = chan->desc;
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cqe = chan->cq + chan->cq_head;
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if (desc) {
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if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) {
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chan->cq_head = (chan->cq_head + 1) %
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hdma_dev->chan_depth;
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hisi_dma_chan_write(hdma_dev->base,
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HISI_DMA_CQ_HEAD_PTR, chan->qp_num,
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chan->cq_head);
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vchan_cookie_complete(&desc->vd);
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} else {
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dev_err(&hdma_dev->pdev->dev, "task error!\n");
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}
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chan->desc = NULL;
|
|
}
|
|
|
|
spin_unlock(&chan->vc.lock);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int hisi_dma_request_qps_irq(struct hisi_dma_dev *hdma_dev)
|
|
{
|
|
struct pci_dev *pdev = hdma_dev->pdev;
|
|
int i, ret;
|
|
|
|
for (i = 0; i < hdma_dev->chan_num; i++) {
|
|
ret = devm_request_irq(&pdev->dev, pci_irq_vector(pdev, i),
|
|
hisi_dma_irq, IRQF_SHARED, "hisi_dma",
|
|
&hdma_dev->chan[i]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* This function enables all hw channels in a device */
|
|
static int hisi_dma_enable_hw_channels(struct hisi_dma_dev *hdma_dev)
|
|
{
|
|
int ret;
|
|
|
|
ret = hisi_dma_alloc_qps_mem(hdma_dev);
|
|
if (ret) {
|
|
dev_err(&hdma_dev->pdev->dev, "fail to allocate qp memory!\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = hisi_dma_request_qps_irq(hdma_dev);
|
|
if (ret) {
|
|
dev_err(&hdma_dev->pdev->dev, "fail to request qp irq!\n");
|
|
return ret;
|
|
}
|
|
|
|
hisi_dma_enable_qps(hdma_dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hisi_dma_disable_hw_channels(void *data)
|
|
{
|
|
hisi_dma_disable_qps(data);
|
|
}
|
|
|
|
static void hisi_dma_set_mode(struct hisi_dma_dev *hdma_dev,
|
|
enum hisi_dma_mode mode)
|
|
{
|
|
writel_relaxed(mode == RC ? 1 : 0, hdma_dev->base + HISI_DMA_MODE);
|
|
}
|
|
|
|
static int hisi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct hisi_dma_dev *hdma_dev;
|
|
struct dma_device *dma_dev;
|
|
int ret;
|
|
|
|
ret = pcim_enable_device(pdev);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable device mem!\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = pcim_iomap_regions(pdev, 1 << PCI_BAR_2, pci_name(pdev));
|
|
if (ret) {
|
|
dev_err(dev, "failed to remap I/O region!\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
|
|
if (ret)
|
|
return ret;
|
|
|
|
hdma_dev = devm_kzalloc(dev, struct_size(hdma_dev, chan, HISI_DMA_CHAN_NUM), GFP_KERNEL);
|
|
if (!hdma_dev)
|
|
return -EINVAL;
|
|
|
|
hdma_dev->base = pcim_iomap_table(pdev)[PCI_BAR_2];
|
|
hdma_dev->pdev = pdev;
|
|
hdma_dev->chan_num = HISI_DMA_CHAN_NUM;
|
|
hdma_dev->chan_depth = HISI_DMA_Q_DEPTH_VAL;
|
|
|
|
pci_set_drvdata(pdev, hdma_dev);
|
|
pci_set_master(pdev);
|
|
|
|
ret = pci_alloc_irq_vectors(pdev, HISI_DMA_MSI_NUM, HISI_DMA_MSI_NUM,
|
|
PCI_IRQ_MSI);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to allocate MSI vectors!\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_add_action_or_reset(dev, hisi_dma_free_irq_vectors, pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dma_dev = &hdma_dev->dma_dev;
|
|
dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
|
|
dma_dev->device_free_chan_resources = hisi_dma_free_chan_resources;
|
|
dma_dev->device_prep_dma_memcpy = hisi_dma_prep_dma_memcpy;
|
|
dma_dev->device_tx_status = hisi_dma_tx_status;
|
|
dma_dev->device_issue_pending = hisi_dma_issue_pending;
|
|
dma_dev->device_terminate_all = hisi_dma_terminate_all;
|
|
dma_dev->device_synchronize = hisi_dma_synchronize;
|
|
dma_dev->directions = BIT(DMA_MEM_TO_MEM);
|
|
dma_dev->dev = dev;
|
|
INIT_LIST_HEAD(&dma_dev->channels);
|
|
|
|
hisi_dma_set_mode(hdma_dev, RC);
|
|
|
|
ret = hisi_dma_enable_hw_channels(hdma_dev);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to enable hw channel!\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_add_action_or_reset(dev, hisi_dma_disable_hw_channels,
|
|
hdma_dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = dmaenginem_async_device_register(dma_dev);
|
|
if (ret < 0)
|
|
dev_err(dev, "failed to register device!\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct pci_device_id hisi_dma_pci_tbl[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa122) },
|
|
{ 0, }
|
|
};
|
|
|
|
static struct pci_driver hisi_dma_pci_driver = {
|
|
.name = "hisi_dma",
|
|
.id_table = hisi_dma_pci_tbl,
|
|
.probe = hisi_dma_probe,
|
|
};
|
|
|
|
module_pci_driver(hisi_dma_pci_driver);
|
|
|
|
MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
|
|
MODULE_AUTHOR("Zhenfa Qiu <qiuzhenfa@hisilicon.com>");
|
|
MODULE_DESCRIPTION("HiSilicon Kunpeng DMA controller driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DEVICE_TABLE(pci, hisi_dma_pci_tbl);
|