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![周琰杰 (Zhou Yanjie)](/assets/img/avatar_default.png)
Enable TCU support for Ingenic X1000, which can be supported by the existing driver. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1584456160-40060-3-git-send-email-zhouyanjie@wanyeetech.com
183 lines
4.9 KiB
C
183 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* JZ47xx SoCs TCU IRQ driver
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* Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/mfd/ingenic-tcu.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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struct ingenic_tcu {
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struct regmap *map;
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struct clk *clk;
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struct irq_domain *domain;
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unsigned int nb_parent_irqs;
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u32 parent_irqs[3];
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};
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static void ingenic_tcu_intc_cascade(struct irq_desc *desc)
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{
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struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
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struct regmap *map = gc->private;
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uint32_t irq_reg, irq_mask;
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unsigned int i;
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regmap_read(map, TCU_REG_TFR, &irq_reg);
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regmap_read(map, TCU_REG_TMR, &irq_mask);
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chained_irq_enter(irq_chip, desc);
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irq_reg &= ~irq_mask;
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for_each_set_bit(i, (unsigned long *)&irq_reg, 32)
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generic_handle_irq(irq_linear_revmap(domain, i));
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chained_irq_exit(irq_chip, desc);
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}
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static void ingenic_tcu_gc_unmask_enable_reg(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct regmap *map = gc->private;
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u32 mask = d->mask;
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irq_gc_lock(gc);
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regmap_write(map, ct->regs.ack, mask);
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regmap_write(map, ct->regs.enable, mask);
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*ct->mask_cache |= mask;
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irq_gc_unlock(gc);
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}
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static void ingenic_tcu_gc_mask_disable_reg(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct regmap *map = gc->private;
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u32 mask = d->mask;
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irq_gc_lock(gc);
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regmap_write(map, ct->regs.disable, mask);
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*ct->mask_cache &= ~mask;
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irq_gc_unlock(gc);
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}
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static void ingenic_tcu_gc_mask_disable_reg_and_ack(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct regmap *map = gc->private;
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u32 mask = d->mask;
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irq_gc_lock(gc);
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regmap_write(map, ct->regs.ack, mask);
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regmap_write(map, ct->regs.disable, mask);
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irq_gc_unlock(gc);
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}
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static int __init ingenic_tcu_irq_init(struct device_node *np,
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struct device_node *parent)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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struct ingenic_tcu *tcu;
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struct regmap *map;
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unsigned int i;
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int ret, irqs;
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map = device_node_to_regmap(np);
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if (IS_ERR(map))
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return PTR_ERR(map);
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tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
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if (!tcu)
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return -ENOMEM;
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tcu->map = map;
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irqs = of_property_count_elems_of_size(np, "interrupts", sizeof(u32));
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if (irqs < 0 || irqs > ARRAY_SIZE(tcu->parent_irqs)) {
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pr_crit("%s: Invalid 'interrupts' property\n", __func__);
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ret = -EINVAL;
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goto err_free_tcu;
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}
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tcu->nb_parent_irqs = irqs;
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tcu->domain = irq_domain_add_linear(np, 32, &irq_generic_chip_ops,
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NULL);
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if (!tcu->domain) {
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ret = -ENOMEM;
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goto err_free_tcu;
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}
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ret = irq_alloc_domain_generic_chips(tcu->domain, 32, 1, "TCU",
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handle_level_irq, 0,
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IRQ_NOPROBE | IRQ_LEVEL, 0);
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if (ret) {
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pr_crit("%s: Invalid 'interrupts' property\n", __func__);
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goto out_domain_remove;
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}
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gc = irq_get_domain_generic_chip(tcu->domain, 0);
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ct = gc->chip_types;
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gc->wake_enabled = IRQ_MSK(32);
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gc->private = tcu->map;
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ct->regs.disable = TCU_REG_TMSR;
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ct->regs.enable = TCU_REG_TMCR;
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ct->regs.ack = TCU_REG_TFCR;
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ct->chip.irq_unmask = ingenic_tcu_gc_unmask_enable_reg;
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ct->chip.irq_mask = ingenic_tcu_gc_mask_disable_reg;
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ct->chip.irq_mask_ack = ingenic_tcu_gc_mask_disable_reg_and_ack;
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ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
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/* Mask all IRQs by default */
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regmap_write(tcu->map, TCU_REG_TMSR, IRQ_MSK(32));
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/*
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* On JZ4740, timer 0 and timer 1 have their own interrupt line;
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* timers 2-7 share one interrupt.
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* On SoCs >= JZ4770, timer 5 has its own interrupt line;
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* timers 0-4 and 6-7 share one single interrupt.
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*
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* To keep things simple, we just register the same handler to
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* all parent interrupts. The handler will properly detect which
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* channel fired the interrupt.
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*/
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for (i = 0; i < irqs; i++) {
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tcu->parent_irqs[i] = irq_of_parse_and_map(np, i);
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if (!tcu->parent_irqs[i]) {
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ret = -EINVAL;
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goto out_unmap_irqs;
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}
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irq_set_chained_handler_and_data(tcu->parent_irqs[i],
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ingenic_tcu_intc_cascade,
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tcu->domain);
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}
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return 0;
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out_unmap_irqs:
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for (; i > 0; i--)
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irq_dispose_mapping(tcu->parent_irqs[i - 1]);
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out_domain_remove:
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irq_domain_remove(tcu->domain);
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err_free_tcu:
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kfree(tcu);
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return ret;
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}
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IRQCHIP_DECLARE(jz4740_tcu_irq, "ingenic,jz4740-tcu", ingenic_tcu_irq_init);
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IRQCHIP_DECLARE(jz4725b_tcu_irq, "ingenic,jz4725b-tcu", ingenic_tcu_irq_init);
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IRQCHIP_DECLARE(jz4770_tcu_irq, "ingenic,jz4770-tcu", ingenic_tcu_irq_init);
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IRQCHIP_DECLARE(x1000_tcu_irq, "ingenic,x1000-tcu", ingenic_tcu_irq_init);
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