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![Rikard Falkeborn](/assets/img/avatar_default.png)
Constify a number of static struct resource. The only usage of the structs are to assign their address to the resources field in the mfd_cell struct. This allows the compiler to put them in read-only memory. Done with the help of Coccinelle. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
676 lines
16 KiB
C
676 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* SGI IOC3 multifunction device driver
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*
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* Copyright (C) 2018, 2019 Thomas Bogendoerfer <tbogendoerfer@suse.de>
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*
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* Based on work by:
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* Stanislaw Skowronek <skylark@unaligned.org>
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* Joshua Kinard <kumba@gentoo.org>
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* Brent Casavant <bcasavan@sgi.com> - IOC4 master driver
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* Pat Gefre <pfg@sgi.com> - IOC3 serial port IRQ demuxer
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/sgi-w1.h>
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#include <linux/rtc/ds1685.h>
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#include <asm/pci/bridge.h>
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#include <asm/sn/ioc3.h>
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#define IOC3_IRQ_SERIAL_A 6
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#define IOC3_IRQ_SERIAL_B 15
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#define IOC3_IRQ_KBD 22
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/* Bitmask for selecting which IRQs are level triggered */
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#define IOC3_LVL_MASK (BIT(IOC3_IRQ_SERIAL_A) | BIT(IOC3_IRQ_SERIAL_B))
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#define M48T35_REG_SIZE 32768 /* size of m48t35 registers */
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/* 1.2 us latency timer (40 cycles at 33 MHz) */
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#define IOC3_LATENCY 40
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struct ioc3_priv_data {
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struct irq_domain *domain;
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struct ioc3 __iomem *regs;
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struct pci_dev *pdev;
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int domain_irq;
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};
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static void ioc3_irq_ack(struct irq_data *d)
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{
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struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
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unsigned int hwirq = irqd_to_hwirq(d);
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writel(BIT(hwirq), &ipd->regs->sio_ir);
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}
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static void ioc3_irq_mask(struct irq_data *d)
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{
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struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
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unsigned int hwirq = irqd_to_hwirq(d);
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writel(BIT(hwirq), &ipd->regs->sio_iec);
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}
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static void ioc3_irq_unmask(struct irq_data *d)
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{
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struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
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unsigned int hwirq = irqd_to_hwirq(d);
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writel(BIT(hwirq), &ipd->regs->sio_ies);
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}
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static struct irq_chip ioc3_irq_chip = {
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.name = "IOC3",
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.irq_ack = ioc3_irq_ack,
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.irq_mask = ioc3_irq_mask,
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.irq_unmask = ioc3_irq_unmask,
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};
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static int ioc3_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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/* Set level IRQs for every interrupt contained in IOC3_LVL_MASK */
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if (BIT(hwirq) & IOC3_LVL_MASK)
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irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_level_irq);
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else
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irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_edge_irq);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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static void ioc3_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops ioc3_irq_domain_ops = {
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.map = ioc3_irq_domain_map,
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.unmap = ioc3_irq_domain_unmap,
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};
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static void ioc3_irq_handler(struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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struct ioc3_priv_data *ipd = domain->host_data;
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struct ioc3 __iomem *regs = ipd->regs;
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u32 pending, mask;
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unsigned int irq;
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pending = readl(®s->sio_ir);
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mask = readl(®s->sio_ies);
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pending &= mask; /* Mask off not enabled interrupts */
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if (pending) {
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irq = irq_find_mapping(domain, __ffs(pending));
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if (irq)
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generic_handle_irq(irq);
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} else {
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spurious_interrupt();
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}
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}
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/*
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* System boards/BaseIOs use more interrupt pins of the bridge ASIC
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* to which the IOC3 is connected. Since the IOC3 MFD driver
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* knows wiring of these extra pins, we use the map_irq function
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* to get interrupts activated
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*/
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static int ioc3_map_irq(struct pci_dev *pdev, int slot, int pin)
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{
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struct pci_host_bridge *hbrg = pci_find_host_bridge(pdev->bus);
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return hbrg->map_irq(pdev, slot, pin);
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}
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static int ioc3_irq_domain_setup(struct ioc3_priv_data *ipd, int irq)
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{
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struct irq_domain *domain;
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struct fwnode_handle *fn;
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fn = irq_domain_alloc_named_fwnode("IOC3");
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if (!fn)
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goto err;
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domain = irq_domain_create_linear(fn, 24, &ioc3_irq_domain_ops, ipd);
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if (!domain) {
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irq_domain_free_fwnode(fn);
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goto err;
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}
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ipd->domain = domain;
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irq_set_chained_handler_and_data(irq, ioc3_irq_handler, domain);
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ipd->domain_irq = irq;
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return 0;
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err:
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dev_err(&ipd->pdev->dev, "irq domain setup failed\n");
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return -ENOMEM;
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}
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static const struct resource ioc3_uarta_resources[] = {
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DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uarta),
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sizeof_field(struct ioc3, sregs.uarta)),
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DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_A)
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};
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static const struct resource ioc3_uartb_resources[] = {
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DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uartb),
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sizeof_field(struct ioc3, sregs.uartb)),
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DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_B)
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};
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static struct mfd_cell ioc3_serial_cells[] = {
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{
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.name = "ioc3-serial8250",
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.resources = ioc3_uarta_resources,
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.num_resources = ARRAY_SIZE(ioc3_uarta_resources),
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},
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{
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.name = "ioc3-serial8250",
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.resources = ioc3_uartb_resources,
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.num_resources = ARRAY_SIZE(ioc3_uartb_resources),
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}
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};
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static int ioc3_serial_setup(struct ioc3_priv_data *ipd)
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{
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int ret;
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/* Set gpio pins for RS232/RS422 mode selection */
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writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL,
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&ipd->regs->gpcr_s);
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/* Select RS232 mode for uart a */
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writel(0, &ipd->regs->gppr[6]);
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/* Select RS232 mode for uart b */
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writel(0, &ipd->regs->gppr[7]);
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/* Switch both ports to 16650 mode */
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writel(readl(&ipd->regs->port_a.sscr) & ~SSCR_DMA_EN,
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&ipd->regs->port_a.sscr);
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writel(readl(&ipd->regs->port_b.sscr) & ~SSCR_DMA_EN,
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&ipd->regs->port_b.sscr);
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udelay(1000); /* Wait until mode switch is done */
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ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
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ioc3_serial_cells, ARRAY_SIZE(ioc3_serial_cells),
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&ipd->pdev->resource[0], 0, ipd->domain);
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if (ret) {
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dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
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return ret;
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}
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return 0;
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}
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static const struct resource ioc3_kbd_resources[] = {
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DEFINE_RES_MEM(offsetof(struct ioc3, serio),
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sizeof_field(struct ioc3, serio)),
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DEFINE_RES_IRQ(IOC3_IRQ_KBD)
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};
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static struct mfd_cell ioc3_kbd_cells[] = {
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{
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.name = "ioc3-kbd",
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.resources = ioc3_kbd_resources,
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.num_resources = ARRAY_SIZE(ioc3_kbd_resources),
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}
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};
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static int ioc3_kbd_setup(struct ioc3_priv_data *ipd)
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{
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int ret;
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ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
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ioc3_kbd_cells, ARRAY_SIZE(ioc3_kbd_cells),
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&ipd->pdev->resource[0], 0, ipd->domain);
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if (ret) {
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dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
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return ret;
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}
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return 0;
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}
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static const struct resource ioc3_eth_resources[] = {
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DEFINE_RES_MEM(offsetof(struct ioc3, eth),
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sizeof_field(struct ioc3, eth)),
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DEFINE_RES_MEM(offsetof(struct ioc3, ssram),
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sizeof_field(struct ioc3, ssram)),
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DEFINE_RES_IRQ(0)
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};
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static const struct resource ioc3_w1_resources[] = {
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DEFINE_RES_MEM(offsetof(struct ioc3, mcr),
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sizeof_field(struct ioc3, mcr)),
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};
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static struct sgi_w1_platform_data ioc3_w1_platform_data;
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static struct mfd_cell ioc3_eth_cells[] = {
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{
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.name = "ioc3-eth",
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.resources = ioc3_eth_resources,
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.num_resources = ARRAY_SIZE(ioc3_eth_resources),
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},
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{
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.name = "sgi_w1",
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.resources = ioc3_w1_resources,
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.num_resources = ARRAY_SIZE(ioc3_w1_resources),
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.platform_data = &ioc3_w1_platform_data,
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.pdata_size = sizeof(ioc3_w1_platform_data),
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}
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};
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static int ioc3_eth_setup(struct ioc3_priv_data *ipd)
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{
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int ret;
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/* Enable One-Wire bus */
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writel(GPCR_MLAN_EN, &ipd->regs->gpcr_s);
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/* Generate unique identifier */
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snprintf(ioc3_w1_platform_data.dev_id,
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sizeof(ioc3_w1_platform_data.dev_id), "ioc3-%012llx",
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ipd->pdev->resource->start);
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ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
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ioc3_eth_cells, ARRAY_SIZE(ioc3_eth_cells),
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&ipd->pdev->resource[0], ipd->pdev->irq, NULL);
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if (ret) {
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dev_err(&ipd->pdev->dev, "Failed to add ETH/W1 subdev\n");
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return ret;
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}
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return 0;
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}
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static const struct resource ioc3_m48t35_resources[] = {
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DEFINE_RES_MEM(IOC3_BYTEBUS_DEV0, M48T35_REG_SIZE)
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};
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static struct mfd_cell ioc3_m48t35_cells[] = {
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{
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.name = "rtc-m48t35",
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.resources = ioc3_m48t35_resources,
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.num_resources = ARRAY_SIZE(ioc3_m48t35_resources),
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}
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};
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static int ioc3_m48t35_setup(struct ioc3_priv_data *ipd)
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{
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int ret;
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ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
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ioc3_m48t35_cells, ARRAY_SIZE(ioc3_m48t35_cells),
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&ipd->pdev->resource[0], 0, ipd->domain);
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if (ret)
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dev_err(&ipd->pdev->dev, "Failed to add M48T35 subdev\n");
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return ret;
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}
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static struct ds1685_rtc_platform_data ip30_rtc_platform_data = {
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.bcd_mode = false,
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.no_irq = false,
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.uie_unsupported = true,
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.access_type = ds1685_reg_indirect,
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};
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static const struct resource ioc3_rtc_ds1685_resources[] = {
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DEFINE_RES_MEM(IOC3_BYTEBUS_DEV1, 1),
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DEFINE_RES_MEM(IOC3_BYTEBUS_DEV2, 1),
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DEFINE_RES_IRQ(0)
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};
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static struct mfd_cell ioc3_ds1685_cells[] = {
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{
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.name = "rtc-ds1685",
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.resources = ioc3_rtc_ds1685_resources,
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.num_resources = ARRAY_SIZE(ioc3_rtc_ds1685_resources),
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.platform_data = &ip30_rtc_platform_data,
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.pdata_size = sizeof(ip30_rtc_platform_data),
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.id = PLATFORM_DEVID_NONE,
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}
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};
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static int ioc3_ds1685_setup(struct ioc3_priv_data *ipd)
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{
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int ret, irq;
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irq = ioc3_map_irq(ipd->pdev, 6, 0);
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ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_ds1685_cells,
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ARRAY_SIZE(ioc3_ds1685_cells),
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&ipd->pdev->resource[0], irq, NULL);
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if (ret)
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dev_err(&ipd->pdev->dev, "Failed to add DS1685 subdev\n");
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return ret;
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};
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static const struct resource ioc3_leds_resources[] = {
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DEFINE_RES_MEM(offsetof(struct ioc3, gppr[0]),
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sizeof_field(struct ioc3, gppr[0])),
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DEFINE_RES_MEM(offsetof(struct ioc3, gppr[1]),
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sizeof_field(struct ioc3, gppr[1])),
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};
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static struct mfd_cell ioc3_led_cells[] = {
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{
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.name = "ip30-leds",
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.resources = ioc3_leds_resources,
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.num_resources = ARRAY_SIZE(ioc3_leds_resources),
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.id = PLATFORM_DEVID_NONE,
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}
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};
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static int ioc3_led_setup(struct ioc3_priv_data *ipd)
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{
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int ret;
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ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_led_cells,
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ARRAY_SIZE(ioc3_led_cells),
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&ipd->pdev->resource[0], 0, ipd->domain);
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if (ret)
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dev_err(&ipd->pdev->dev, "Failed to add LED subdev\n");
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return ret;
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}
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static int ip27_baseio_setup(struct ioc3_priv_data *ipd)
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{
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int ret, io_irq;
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io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
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PCI_INTERRUPT_INTB);
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ret = ioc3_irq_domain_setup(ipd, io_irq);
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if (ret)
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return ret;
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ret = ioc3_eth_setup(ipd);
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if (ret)
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return ret;
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ret = ioc3_serial_setup(ipd);
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if (ret)
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return ret;
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return ioc3_m48t35_setup(ipd);
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}
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static int ip27_baseio6g_setup(struct ioc3_priv_data *ipd)
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{
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int ret, io_irq;
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io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
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PCI_INTERRUPT_INTB);
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ret = ioc3_irq_domain_setup(ipd, io_irq);
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if (ret)
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return ret;
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ret = ioc3_eth_setup(ipd);
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if (ret)
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return ret;
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ret = ioc3_serial_setup(ipd);
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if (ret)
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return ret;
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ret = ioc3_m48t35_setup(ipd);
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if (ret)
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return ret;
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return ioc3_kbd_setup(ipd);
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}
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static int ip27_mio_setup(struct ioc3_priv_data *ipd)
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{
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int ret;
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ret = ioc3_irq_domain_setup(ipd, ipd->pdev->irq);
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if (ret)
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return ret;
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ret = ioc3_serial_setup(ipd);
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if (ret)
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return ret;
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return ioc3_kbd_setup(ipd);
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}
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static int ip30_sysboard_setup(struct ioc3_priv_data *ipd)
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{
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int ret, io_irq;
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io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
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PCI_INTERRUPT_INTB);
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ret = ioc3_irq_domain_setup(ipd, io_irq);
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if (ret)
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return ret;
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ret = ioc3_eth_setup(ipd);
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if (ret)
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return ret;
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ret = ioc3_serial_setup(ipd);
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if (ret)
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return ret;
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ret = ioc3_kbd_setup(ipd);
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if (ret)
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return ret;
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ret = ioc3_ds1685_setup(ipd);
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if (ret)
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return ret;
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return ioc3_led_setup(ipd);
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}
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static int ioc3_menet_setup(struct ioc3_priv_data *ipd)
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{
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|
int ret, io_irq;
|
|
|
|
io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
|
|
PCI_INTERRUPT_INTB);
|
|
ret = ioc3_irq_domain_setup(ipd, io_irq);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ioc3_eth_setup(ipd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return ioc3_serial_setup(ipd);
|
|
}
|
|
|
|
static int ioc3_menet4_setup(struct ioc3_priv_data *ipd)
|
|
{
|
|
return ioc3_eth_setup(ipd);
|
|
}
|
|
|
|
static int ioc3_cad_duo_setup(struct ioc3_priv_data *ipd)
|
|
{
|
|
int ret, io_irq;
|
|
|
|
io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
|
|
PCI_INTERRUPT_INTB);
|
|
ret = ioc3_irq_domain_setup(ipd, io_irq);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ioc3_eth_setup(ipd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return ioc3_kbd_setup(ipd);
|
|
}
|
|
|
|
/* Helper macro for filling ioc3_info array */
|
|
#define IOC3_SID(_name, _sid, _setup) \
|
|
{ \
|
|
.name = _name, \
|
|
.sid = PCI_VENDOR_ID_SGI | (IOC3_SUBSYS_ ## _sid << 16), \
|
|
.setup = _setup, \
|
|
}
|
|
|
|
static struct {
|
|
const char *name;
|
|
u32 sid;
|
|
int (*setup)(struct ioc3_priv_data *ipd);
|
|
} ioc3_infos[] = {
|
|
IOC3_SID("IP27 BaseIO6G", IP27_BASEIO6G, &ip27_baseio6g_setup),
|
|
IOC3_SID("IP27 MIO", IP27_MIO, &ip27_mio_setup),
|
|
IOC3_SID("IP27 BaseIO", IP27_BASEIO, &ip27_baseio_setup),
|
|
IOC3_SID("IP29 System Board", IP29_SYSBOARD, &ip27_baseio6g_setup),
|
|
IOC3_SID("IP30 System Board", IP30_SYSBOARD, &ip30_sysboard_setup),
|
|
IOC3_SID("MENET", MENET, &ioc3_menet_setup),
|
|
IOC3_SID("MENET4", MENET4, &ioc3_menet4_setup)
|
|
};
|
|
#undef IOC3_SID
|
|
|
|
static int ioc3_setup(struct ioc3_priv_data *ipd)
|
|
{
|
|
u32 sid;
|
|
int i;
|
|
|
|
/* Clear IRQs */
|
|
writel(~0, &ipd->regs->sio_iec);
|
|
writel(~0, &ipd->regs->sio_ir);
|
|
writel(0, &ipd->regs->eth.eier);
|
|
writel(~0, &ipd->regs->eth.eisr);
|
|
|
|
/* Read subsystem vendor id and subsystem id */
|
|
pci_read_config_dword(ipd->pdev, PCI_SUBSYSTEM_VENDOR_ID, &sid);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ioc3_infos); i++)
|
|
if (sid == ioc3_infos[i].sid) {
|
|
pr_info("ioc3: %s\n", ioc3_infos[i].name);
|
|
return ioc3_infos[i].setup(ipd);
|
|
}
|
|
|
|
/* Treat everything not identified by PCI subid as CAD DUO */
|
|
pr_info("ioc3: CAD DUO\n");
|
|
return ioc3_cad_duo_setup(ipd);
|
|
}
|
|
|
|
static int ioc3_mfd_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *pci_id)
|
|
{
|
|
struct ioc3_priv_data *ipd;
|
|
struct ioc3 __iomem *regs;
|
|
int ret;
|
|
|
|
ret = pci_enable_device(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, IOC3_LATENCY);
|
|
pci_set_master(pdev);
|
|
|
|
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
|
|
if (ret) {
|
|
pr_err("%s: No usable DMA configuration, aborting.\n",
|
|
pci_name(pdev));
|
|
goto out_disable_device;
|
|
}
|
|
|
|
/* Set up per-IOC3 data */
|
|
ipd = devm_kzalloc(&pdev->dev, sizeof(struct ioc3_priv_data),
|
|
GFP_KERNEL);
|
|
if (!ipd) {
|
|
ret = -ENOMEM;
|
|
goto out_disable_device;
|
|
}
|
|
ipd->pdev = pdev;
|
|
|
|
/*
|
|
* Map all IOC3 registers. These are shared between subdevices
|
|
* so the main IOC3 module manages them.
|
|
*/
|
|
regs = pci_ioremap_bar(pdev, 0);
|
|
if (!regs) {
|
|
dev_warn(&pdev->dev, "ioc3: Unable to remap PCI BAR for %s.\n",
|
|
pci_name(pdev));
|
|
ret = -ENOMEM;
|
|
goto out_disable_device;
|
|
}
|
|
ipd->regs = regs;
|
|
|
|
/* Track PCI-device specific data */
|
|
pci_set_drvdata(pdev, ipd);
|
|
|
|
ret = ioc3_setup(ipd);
|
|
if (ret) {
|
|
/* Remove all already added MFD devices */
|
|
mfd_remove_devices(&ipd->pdev->dev);
|
|
if (ipd->domain) {
|
|
struct fwnode_handle *fn = ipd->domain->fwnode;
|
|
|
|
irq_domain_remove(ipd->domain);
|
|
irq_domain_free_fwnode(fn);
|
|
free_irq(ipd->domain_irq, (void *)ipd);
|
|
}
|
|
pci_iounmap(pdev, regs);
|
|
goto out_disable_device;
|
|
}
|
|
|
|
return 0;
|
|
|
|
out_disable_device:
|
|
pci_disable_device(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static void ioc3_mfd_remove(struct pci_dev *pdev)
|
|
{
|
|
struct ioc3_priv_data *ipd;
|
|
|
|
ipd = pci_get_drvdata(pdev);
|
|
|
|
/* Clear and disable all IRQs */
|
|
writel(~0, &ipd->regs->sio_iec);
|
|
writel(~0, &ipd->regs->sio_ir);
|
|
|
|
/* Release resources */
|
|
mfd_remove_devices(&ipd->pdev->dev);
|
|
if (ipd->domain) {
|
|
struct fwnode_handle *fn = ipd->domain->fwnode;
|
|
|
|
irq_domain_remove(ipd->domain);
|
|
irq_domain_free_fwnode(fn);
|
|
free_irq(ipd->domain_irq, (void *)ipd);
|
|
}
|
|
pci_iounmap(pdev, ipd->regs);
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
static struct pci_device_id ioc3_mfd_id_table[] = {
|
|
{ PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
|
|
{ 0, },
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, ioc3_mfd_id_table);
|
|
|
|
static struct pci_driver ioc3_mfd_driver = {
|
|
.name = "IOC3",
|
|
.id_table = ioc3_mfd_id_table,
|
|
.probe = ioc3_mfd_probe,
|
|
.remove = ioc3_mfd_remove,
|
|
};
|
|
|
|
module_pci_driver(ioc3_mfd_driver);
|
|
|
|
MODULE_AUTHOR("Thomas Bogendoerfer <tbogendoerfer@suse.de>");
|
|
MODULE_DESCRIPTION("SGI IOC3 MFD driver");
|
|
MODULE_LICENSE("GPL v2");
|