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![Uwe Kleine-König](/assets/img/avatar_default.png)
The driver used this construct: #define KMB_PWM_LEADIN_MASK GENMASK(30, 0) static inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask, u32 val, u32 offset) { u32 buff = readl(priv->base + offset); buff = u32_replace_bits(buff, val, mask); writel(buff, priv->base + offset); } ... keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0, KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); With CONFIG_CC_OPTIMIZE_FOR_SIZE the compiler (here: gcc 10.2.0) this triggers: In file included from /home/uwe/gsrc/linux/drivers/pwm/pwm-keembay.c:16: In function ‘field_multiplier’, inlined from ‘keembay_pwm_update_bits’ at /home/uwe/gsrc/linux/include/linux/bitfield.h:124:17: /home/uwe/gsrc/linux/include/linux/bitfield.h:119:3: error: call to ‘__bad_mask’ declared with attribute error: bad bitfield mask 119 | __bad_mask(); | ^~~~~~~~~~~~ In function ‘field_multiplier’, inlined from ‘keembay_pwm_update_bits’ at /home/uwe/gsrc/linux/include/linux/bitfield.h:154:1: /home/uwe/gsrc/linux/include/linux/bitfield.h:119:3: error: call to ‘__bad_mask’ declared with attribute error: bad bitfield mask 119 | __bad_mask(); | ^~~~~~~~~~~~ The compiler doesn't seem to be able to notice that with field being 0x3ffffff the expression if ((field | (field - 1)) & ((field | (field - 1)) + 1)) __bad_mask(); can be optimized away. So use __always_inline and document the problem in a comment to fix this. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
245 lines
6.3 KiB
C
245 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Keem Bay PWM driver
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*
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* Copyright (C) 2020 Intel Corporation
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* Authors: Lai Poey Seng <poey.seng.lai@intel.com>
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* Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
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*
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* Limitations:
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* - Upon disabling a channel, the currently running
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* period will not be completed. However, upon
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* reconfiguration of the duty cycle/period, the
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* currently running period will be completed first.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#define KMB_TOTAL_PWM_CHANNELS 6
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#define KMB_PWM_COUNT_MAX U16_MAX
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#define KMB_PWM_EN_BIT BIT(31)
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/* Mask */
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#define KMB_PWM_HIGH_MASK GENMASK(31, 16)
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#define KMB_PWM_LOW_MASK GENMASK(15, 0)
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#define KMB_PWM_LEADIN_MASK GENMASK(30, 0)
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/* PWM Register offset */
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#define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch))
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#define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch))
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struct keembay_pwm {
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struct pwm_chip chip;
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struct device *dev;
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struct clk *clk;
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void __iomem *base;
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};
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static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip)
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{
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return container_of(chip, struct keembay_pwm, chip);
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}
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static void keembay_clk_unprepare(void *data)
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{
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clk_disable_unprepare(data);
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}
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static int keembay_clk_enable(struct device *dev, struct clk *clk)
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{
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int ret;
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk);
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}
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/*
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* With gcc 10, CONFIG_CC_OPTIMIZE_FOR_SIZE and only "inline" instead of
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* "__always_inline" this fails to compile because the compiler doesn't notice
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* for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.
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*/
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static __always_inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask,
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u32 val, u32 offset)
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{
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u32 buff = readl(priv->base + offset);
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buff = u32_replace_bits(buff, val, mask);
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writel(buff, priv->base + offset);
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}
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static void keembay_pwm_enable(struct keembay_pwm *priv, int ch)
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{
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keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1,
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KMB_PWM_LEADIN_OFFSET(ch));
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}
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static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)
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{
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keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0,
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KMB_PWM_LEADIN_OFFSET(ch));
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}
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static void keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
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unsigned long long high, low;
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unsigned long clk_rate;
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u32 highlow;
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clk_rate = clk_get_rate(priv->clk);
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/* Read channel enabled status */
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highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
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if (highlow & KMB_PWM_EN_BIT)
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state->enabled = true;
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else
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state->enabled = false;
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/* Read period and duty cycle */
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highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
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low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;
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high = FIELD_GET(KMB_PWM_HIGH_MASK, highlow) * NSEC_PER_SEC;
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state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);
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state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);
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state->polarity = PWM_POLARITY_NORMAL;
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}
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static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
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struct pwm_state current_state;
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unsigned long long div;
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unsigned long clk_rate;
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u32 pwm_count = 0;
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u16 high, low;
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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/*
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* Configure the pwm repeat count as infinite at (15:0) and leadin
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* low time as 0 at (30:16), which is in terms of clock cycles.
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*/
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keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0,
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KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
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keembay_pwm_get_state(chip, pwm, ¤t_state);
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if (!state->enabled) {
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if (current_state.enabled)
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keembay_pwm_disable(priv, pwm->hwpwm);
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return 0;
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}
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/*
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* The upper 16 bits and lower 16 bits of the KMB_PWM_HIGHLOW_OFFSET
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* register contain the high time and low time of waveform accordingly.
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* All the values are in terms of clock cycles.
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*/
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clk_rate = clk_get_rate(priv->clk);
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div = clk_rate * state->duty_cycle;
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div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
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if (div > KMB_PWM_COUNT_MAX)
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return -ERANGE;
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high = div;
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div = clk_rate * state->period;
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div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
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div = div - high;
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if (div > KMB_PWM_COUNT_MAX)
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return -ERANGE;
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low = div;
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pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, high) |
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FIELD_PREP(KMB_PWM_LOW_MASK, low);
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writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
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if (state->enabled && !current_state.enabled)
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keembay_pwm_enable(priv, pwm->hwpwm);
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return 0;
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}
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static const struct pwm_ops keembay_pwm_ops = {
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.owner = THIS_MODULE,
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.apply = keembay_pwm_apply,
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.get_state = keembay_pwm_get_state,
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};
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static int keembay_pwm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct keembay_pwm *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk))
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return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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ret = keembay_clk_enable(dev, priv->clk);
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if (ret)
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return ret;
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priv->chip.base = -1;
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priv->chip.dev = dev;
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priv->chip.ops = &keembay_pwm_ops;
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priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS;
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ret = pwmchip_add(&priv->chip);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
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platform_set_drvdata(pdev, priv);
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return 0;
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}
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static int keembay_pwm_remove(struct platform_device *pdev)
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{
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struct keembay_pwm *priv = platform_get_drvdata(pdev);
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return pwmchip_remove(&priv->chip);
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}
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static const struct of_device_id keembay_pwm_of_match[] = {
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{ .compatible = "intel,keembay-pwm" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, keembay_pwm_of_match);
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static struct platform_driver keembay_pwm_driver = {
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.probe = keembay_pwm_probe,
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.remove = keembay_pwm_remove,
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.driver = {
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.name = "pwm-keembay",
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.of_match_table = keembay_pwm_of_match,
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},
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};
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module_platform_driver(keembay_pwm_driver);
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MODULE_ALIAS("platform:pwm-keembay");
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MODULE_DESCRIPTION("Intel Keem Bay PWM driver");
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MODULE_LICENSE("GPL v2");
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