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![]() Include: - Update for Litex SoC controller to support wider width registers as well as reset. - Refactor SMP code to use device tree to define possible cpus. - Updates build including generating vmlinux.bin -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmA5bOcACgkQw7McLV5m J+QzlBAAl3kfYayGs286Ol5XDHQynFLkfUkGIrD8T+aHjjZS2DRJOAwoGbE+htv6 Nt6rXciHi9FNSgTf+nuTm/aQ8qSgFlsYB0AQBjLA193Og/3+G0ifQHcMoDKKRwj/ u/gqD9geGrsgVRAxqNQ18wBqX+rBPajq8+Mtjg3/ikJfkFc0GqugqevpIRNC7gN4 PmttAlOhecxFrJ1H4O4qqwctooPAIZJgRXYK8FiOBvyQXOkBmPmuodh1FhdR+jEZ /My5PQ6vYgCaXh9FuckX2xf0B3iV5+T6FFoGMPTERjz0ntglHhFLA7P18o8gsaXT vUQfT9gtoR9OckmUUxXyXlF3oZft4KouMwp04+WWaiOX52nWLXJ4Jh3GV9UbprJl TwlnOkUtQOttRIuIkKnbzDITY91RLPjH5hlO2Suc2nKG6ExNeHNqt+btn7KoFRy9 BDqRZKppBcz2PUSfHo+kC9MDM6/D4ZYlTlprW9b/U7Aa2xfVWa5KkxamiCT6gVec 8/y+8VnOU4JGl+KcAr61FoBCHgWqAOVe3XLO3oyvdpVDChNtcFl7d2zYiqoS+9fc HDR2Xivr+qClAUpFo+JeLKfISl0j/5lu1+4t7bA6fMunv3ObFHIJUKKCFBIugLu6 j9nM2F2fqDmvh6xGSFp6bP9PIa6Rmk79EA75R0F4HINU1rnnPKI= =IW6A -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://github.com/openrisc/linux Pull OpenRISC updates from Stafford Horne: - Update for Litex SoC controller to support wider width registers as well as reset. - Refactor SMP code to use device tree to define possible cpus. - Update build including generating vmlinux.bin * tag 'for-linus' of git://github.com/openrisc/linux: openrisc: Use devicetree to determine present cpus drivers/soc/litex: Add restart handler openrisc: add arch/openrisc/Kbuild drivers/soc/litex: make 'litex_[set|get]_reg()' methods private drivers/soc/litex: support 32-bit subregisters, 64-bit CPUs drivers/soc/litex: s/LITEX_REG_SIZE/LITEX_SUBREG_ALIGN/g drivers/soc/litex: separate MMIO from subregister offset calculation drivers/soc/litex: move generic accessors to litex.h openrisc: restart: Call common handlers before hanging openrisc: Add vmlinux.bin target |
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litex_soc_ctrl.c | ||
Makefile |