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![Crystal Guo](/assets/img/avatar_default.png)
Add support for watchdog device found in MT8192 SoC Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20201014131936.20584-5-crystal.guo@mediatek.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
374 lines
8.9 KiB
C
374 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Mediatek Watchdog Driver
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*
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* Copyright (C) 2014 Matthias Brugger
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*
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* Matthias Brugger <matthias.bgg@gmail.com>
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*
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* Based on sunxi_wdt.c
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*/
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#include <dt-bindings/reset-controller/mt2712-resets.h>
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#include <dt-bindings/reset-controller/mt8183-resets.h>
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#include <dt-bindings/reset-controller/mt8192-resets.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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#define WDT_MAX_TIMEOUT 31
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#define WDT_MIN_TIMEOUT 1
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#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
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#define WDT_LENGTH 0x04
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#define WDT_LENGTH_KEY 0x8
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#define WDT_RST 0x08
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#define WDT_RST_RELOAD 0x1971
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#define WDT_MODE 0x00
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#define WDT_MODE_EN (1 << 0)
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#define WDT_MODE_EXT_POL_LOW (0 << 1)
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#define WDT_MODE_EXT_POL_HIGH (1 << 1)
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#define WDT_MODE_EXRST_EN (1 << 2)
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#define WDT_MODE_IRQ_EN (1 << 3)
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#define WDT_MODE_AUTO_START (1 << 4)
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#define WDT_MODE_DUAL_EN (1 << 6)
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#define WDT_MODE_KEY 0x22000000
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#define WDT_SWRST 0x14
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#define WDT_SWRST_KEY 0x1209
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#define WDT_SWSYSRST 0x18U
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#define WDT_SWSYS_RST_KEY 0x88000000
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#define DRV_NAME "mtk-wdt"
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#define DRV_VERSION "1.0"
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static bool nowayout = WATCHDOG_NOWAYOUT;
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static unsigned int timeout;
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struct mtk_wdt_dev {
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struct watchdog_device wdt_dev;
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void __iomem *wdt_base;
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spinlock_t lock; /* protects WDT_SWSYSRST reg */
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struct reset_controller_dev rcdev;
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};
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struct mtk_wdt_data {
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int toprgu_sw_rst_num;
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};
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static const struct mtk_wdt_data mt2712_data = {
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.toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
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};
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static const struct mtk_wdt_data mt8183_data = {
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.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
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};
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static const struct mtk_wdt_data mt8192_data = {
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.toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
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};
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static int toprgu_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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unsigned int tmp;
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unsigned long flags;
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struct mtk_wdt_dev *data =
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container_of(rcdev, struct mtk_wdt_dev, rcdev);
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spin_lock_irqsave(&data->lock, flags);
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tmp = readl(data->wdt_base + WDT_SWSYSRST);
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if (assert)
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tmp |= BIT(id);
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else
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tmp &= ~BIT(id);
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tmp |= WDT_SWSYS_RST_KEY;
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writel(tmp, data->wdt_base + WDT_SWSYSRST);
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return toprgu_reset_update(rcdev, id, true);
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}
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static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return toprgu_reset_update(rcdev, id, false);
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}
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static int toprgu_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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int ret;
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ret = toprgu_reset_assert(rcdev, id);
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if (ret)
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return ret;
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return toprgu_reset_deassert(rcdev, id);
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}
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static const struct reset_control_ops toprgu_reset_ops = {
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.assert = toprgu_reset_assert,
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.deassert = toprgu_reset_deassert,
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.reset = toprgu_reset,
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};
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static int toprgu_register_reset_controller(struct platform_device *pdev,
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int rst_num)
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{
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int ret;
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struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
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spin_lock_init(&mtk_wdt->lock);
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mtk_wdt->rcdev.owner = THIS_MODULE;
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mtk_wdt->rcdev.nr_resets = rst_num;
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mtk_wdt->rcdev.ops = &toprgu_reset_ops;
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mtk_wdt->rcdev.of_node = pdev->dev.of_node;
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ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
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if (ret != 0)
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dev_err(&pdev->dev,
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"couldn't register wdt reset controller: %d\n", ret);
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return ret;
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}
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static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
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unsigned long action, void *data)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base;
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wdt_base = mtk_wdt->wdt_base;
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while (1) {
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writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
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mdelay(5);
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}
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return 0;
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}
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static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base = mtk_wdt->wdt_base;
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iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
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return 0;
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}
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static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
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unsigned int timeout)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base = mtk_wdt->wdt_base;
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u32 reg;
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wdt_dev->timeout = timeout;
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/*
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* One bit is the value of 512 ticks
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* The clock has 32 KHz
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*/
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reg = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
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iowrite32(reg, wdt_base + WDT_LENGTH);
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mtk_wdt_ping(wdt_dev);
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return 0;
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}
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static void mtk_wdt_init(struct watchdog_device *wdt_dev)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base;
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wdt_base = mtk_wdt->wdt_base;
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if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
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set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
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mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
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}
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}
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static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base = mtk_wdt->wdt_base;
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u32 reg;
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reg = readl(wdt_base + WDT_MODE);
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reg &= ~WDT_MODE_EN;
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reg |= WDT_MODE_KEY;
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iowrite32(reg, wdt_base + WDT_MODE);
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return 0;
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}
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static int mtk_wdt_start(struct watchdog_device *wdt_dev)
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{
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u32 reg;
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base = mtk_wdt->wdt_base;
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int ret;
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ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
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if (ret < 0)
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return ret;
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reg = ioread32(wdt_base + WDT_MODE);
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reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
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reg |= (WDT_MODE_EN | WDT_MODE_KEY);
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iowrite32(reg, wdt_base + WDT_MODE);
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return 0;
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}
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static const struct watchdog_info mtk_wdt_info = {
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.identity = DRV_NAME,
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.options = WDIOF_SETTIMEOUT |
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WDIOF_KEEPALIVEPING |
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WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_ops mtk_wdt_ops = {
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.owner = THIS_MODULE,
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.start = mtk_wdt_start,
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.stop = mtk_wdt_stop,
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.ping = mtk_wdt_ping,
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.set_timeout = mtk_wdt_set_timeout,
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.restart = mtk_wdt_restart,
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};
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static int mtk_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_wdt_dev *mtk_wdt;
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const struct mtk_wdt_data *wdt_data;
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int err;
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mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
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if (!mtk_wdt)
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return -ENOMEM;
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platform_set_drvdata(pdev, mtk_wdt);
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mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mtk_wdt->wdt_base))
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return PTR_ERR(mtk_wdt->wdt_base);
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mtk_wdt->wdt_dev.info = &mtk_wdt_info;
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mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
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mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
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mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
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mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
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mtk_wdt->wdt_dev.parent = dev;
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watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
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watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
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watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
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watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
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mtk_wdt_init(&mtk_wdt->wdt_dev);
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watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
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err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
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if (unlikely(err))
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return err;
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dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
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mtk_wdt->wdt_dev.timeout, nowayout);
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wdt_data = of_device_get_match_data(dev);
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if (wdt_data) {
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err = toprgu_register_reset_controller(pdev,
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wdt_data->toprgu_sw_rst_num);
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if (err)
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return err;
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}
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int mtk_wdt_suspend(struct device *dev)
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{
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struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
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if (watchdog_active(&mtk_wdt->wdt_dev))
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mtk_wdt_stop(&mtk_wdt->wdt_dev);
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return 0;
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}
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static int mtk_wdt_resume(struct device *dev)
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{
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struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
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if (watchdog_active(&mtk_wdt->wdt_dev)) {
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mtk_wdt_start(&mtk_wdt->wdt_dev);
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mtk_wdt_ping(&mtk_wdt->wdt_dev);
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}
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return 0;
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}
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#endif
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static const struct of_device_id mtk_wdt_dt_ids[] = {
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{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
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{ .compatible = "mediatek,mt6589-wdt" },
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{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
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{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
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static const struct dev_pm_ops mtk_wdt_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
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mtk_wdt_resume)
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};
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static struct platform_driver mtk_wdt_driver = {
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.probe = mtk_wdt_probe,
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.driver = {
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.name = DRV_NAME,
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.pm = &mtk_wdt_pm_ops,
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.of_match_table = mtk_wdt_dt_ids,
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},
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};
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module_platform_driver(mtk_wdt_driver);
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module_param(timeout, uint, 0);
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MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
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MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
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MODULE_VERSION(DRV_VERSION);
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