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6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
73 lines
1.6 KiB
C
73 lines
1.6 KiB
C
/*
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* PPC440GP system library
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*
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* Matt Porter <mporter@mvista.com>
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* Copyright 2002-2003 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/types.h>
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#include <asm/reg.h>
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#include <asm/ibm44x.h>
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#include <asm/mmu.h>
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/*
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* Calculate 440GP clocks
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*/
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void __init ibm440gp_get_clocks(struct ibm44x_clocks* p,
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unsigned int sys_clk,
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unsigned int ser_clk)
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{
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u32 cpc0_sys0 = mfdcr(DCRN_CPC0_SYS0);
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u32 cpc0_cr0 = mfdcr(DCRN_CPC0_CR0);
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u32 opdv = ((cpc0_sys0 >> 10) & 0x3) + 1;
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u32 epdv = ((cpc0_sys0 >> 8) & 0x3) + 1;
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if (cpc0_sys0 & 0x2){
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/* Bypass system PLL */
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p->cpu = p->plb = sys_clk;
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}
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else {
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u32 fbdv, fwdva, fwdvb, m, vco;
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fbdv = (cpc0_sys0 >> 18) & 0x0f;
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if (!fbdv)
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fbdv = 16;
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fwdva = 8 - ((cpc0_sys0 >> 15) & 0x7);
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fwdvb = 8 - ((cpc0_sys0 >> 12) & 0x7);
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/* Feedback path */
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if (cpc0_sys0 & 0x00000080){
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/* PerClk */
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m = fwdvb * opdv * epdv;
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}
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else {
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/* CPU clock */
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m = fbdv * fwdva;
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}
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vco = sys_clk * m;
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p->cpu = vco / fwdva;
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p->plb = vco / fwdvb;
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}
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p->opb = p->plb / opdv;
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p->ebc = p->opb / epdv;
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if (cpc0_cr0 & 0x00400000){
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/* External UART clock */
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p->uart0 = p->uart1 = ser_clk;
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}
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else {
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/* Internal UART clock */
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u32 uart_div = ((cpc0_cr0 >> 16) & 0x1f) + 1;
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p->uart0 = p->uart1 = p->plb / uart_div;
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}
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}
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