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![Suresh Siddha](/assets/img/avatar_default.png)
This will pave the way for each apic driver to be self-contained and eliminate the need for apic_probe[]. Order in which apic drivers are listed in the .apicdrivers section is important, as this determines the apic probe order. And this is enforced by the ordering of apic driver files in the Makefile and the macros apic_driver()/apic_drivers(). Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Tested-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: steiner@sgi.com Cc: gorcunov@openvz.org Cc: yinghai@kernel.org Link: http://lkml.kernel.org/r/20110521005526.068775085@sbsiddha-MOBL3.sc.intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
868 lines
22 KiB
C
868 lines
22 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV APIC functions (note: not an Intel compatible APIC)
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*
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* Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/cpumask.h>
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#include <linux/hardirq.h>
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#include <linux/proc_fs.h>
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#include <linux/threads.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/ctype.h>
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#include <linux/sched.h>
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#include <linux/timer.h>
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#include <linux/slab.h>
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <linux/kdebug.h>
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#include <linux/delay.h>
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#include <linux/crash_dump.h>
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#include <asm/uv/uv_mmrs.h>
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#include <asm/uv/uv_hub.h>
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#include <asm/current.h>
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#include <asm/pgtable.h>
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#include <asm/uv/bios.h>
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#include <asm/uv/uv.h>
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#include <asm/apic.h>
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#include <asm/ipi.h>
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#include <asm/smp.h>
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#include <asm/x86_init.h>
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#include <asm/emergency-restart.h>
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#include <asm/nmi.h>
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/* BMC sets a bit this MMR non-zero before sending an NMI */
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#define UVH_NMI_MMR UVH_SCRATCH5
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#define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8)
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#define UV_NMI_PENDING_MASK (1UL << 63)
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DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);
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DEFINE_PER_CPU(int, x2apic_extra_bits);
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#define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
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static enum uv_system_type uv_system_type;
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static u64 gru_start_paddr, gru_end_paddr;
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static union uvh_apicid uvh_apicid;
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int uv_min_hub_revision_id;
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EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
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unsigned int uv_apicid_hibits;
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EXPORT_SYMBOL_GPL(uv_apicid_hibits);
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static DEFINE_SPINLOCK(uv_nmi_lock);
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static unsigned long __init uv_early_read_mmr(unsigned long addr)
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{
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unsigned long val, *mmr;
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mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
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val = *mmr;
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early_iounmap(mmr, sizeof(*mmr));
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return val;
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}
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static inline bool is_GRU_range(u64 start, u64 end)
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{
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return start >= gru_start_paddr && end <= gru_end_paddr;
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}
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static bool uv_is_untracked_pat_range(u64 start, u64 end)
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{
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return is_ISA_range(start, end) || is_GRU_range(start, end);
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}
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static int __init early_get_pnodeid(void)
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{
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union uvh_node_id_u node_id;
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union uvh_rh_gam_config_mmr_u m_n_config;
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int pnode;
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/* Currently, all blades have same revision number */
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node_id.v = uv_early_read_mmr(UVH_NODE_ID);
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m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
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uv_min_hub_revision_id = node_id.s.revision;
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pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
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return pnode;
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}
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static void __init early_get_apic_pnode_shift(void)
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{
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uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
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if (!uvh_apicid.v)
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/*
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* Old bios, use default value
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*/
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uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
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}
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/*
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* Add an extra bit as dictated by bios to the destination apicid of
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* interrupts potentially passing through the UV HUB. This prevents
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* a deadlock between interrupts and IO port operations.
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*/
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static void __init uv_set_apicid_hibit(void)
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{
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union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
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apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK);
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uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
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}
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static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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int pnodeid;
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if (!strcmp(oem_id, "SGI")) {
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pnodeid = early_get_pnodeid();
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early_get_apic_pnode_shift();
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x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
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x86_platform.nmi_init = uv_nmi_init;
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if (!strcmp(oem_table_id, "UVL"))
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uv_system_type = UV_LEGACY_APIC;
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else if (!strcmp(oem_table_id, "UVX"))
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uv_system_type = UV_X2APIC;
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else if (!strcmp(oem_table_id, "UVH")) {
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__this_cpu_write(x2apic_extra_bits,
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pnodeid << uvh_apicid.s.pnode_shift);
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uv_system_type = UV_NON_UNIQUE_APIC;
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uv_set_apicid_hibit();
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return 1;
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}
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}
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return 0;
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}
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enum uv_system_type get_uv_system_type(void)
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{
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return uv_system_type;
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}
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int is_uv_system(void)
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{
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return uv_system_type != UV_NONE;
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}
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EXPORT_SYMBOL_GPL(is_uv_system);
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DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
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EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
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struct uv_blade_info *uv_blade_info;
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EXPORT_SYMBOL_GPL(uv_blade_info);
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short *uv_node_to_blade;
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EXPORT_SYMBOL_GPL(uv_node_to_blade);
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short *uv_cpu_to_blade;
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EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
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short uv_possible_blades;
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EXPORT_SYMBOL_GPL(uv_possible_blades);
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unsigned long sn_rtc_cycles_per_second;
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EXPORT_SYMBOL(sn_rtc_cycles_per_second);
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static const struct cpumask *uv_target_cpus(void)
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{
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return cpu_online_mask;
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}
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static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
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{
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#ifdef CONFIG_SMP
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unsigned long val;
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int pnode;
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pnode = uv_apicid_to_pnode(phys_apicid);
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phys_apicid |= uv_apicid_hibits;
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val = (1UL << UVH_IPI_INT_SEND_SHFT) |
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(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
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((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
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APIC_DM_INIT;
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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mdelay(10);
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val = (1UL << UVH_IPI_INT_SEND_SHFT) |
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(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
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((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
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APIC_DM_STARTUP;
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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atomic_set(&init_deasserted, 1);
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#endif
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return 0;
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}
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static void uv_send_IPI_one(int cpu, int vector)
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{
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unsigned long apicid;
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int pnode;
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apicid = per_cpu(x86_cpu_to_apicid, cpu);
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pnode = uv_apicid_to_pnode(apicid);
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uv_hub_send_ipi(pnode, apicid, vector);
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}
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static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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unsigned int cpu;
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for_each_cpu(cpu, mask)
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uv_send_IPI_one(cpu, vector);
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}
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static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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for_each_cpu(cpu, mask) {
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if (cpu != this_cpu)
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uv_send_IPI_one(cpu, vector);
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}
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}
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static void uv_send_IPI_allbutself(int vector)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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for_each_online_cpu(cpu) {
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if (cpu != this_cpu)
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uv_send_IPI_one(cpu, vector);
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}
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}
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static void uv_send_IPI_all(int vector)
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{
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uv_send_IPI_mask(cpu_online_mask, vector);
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}
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static int uv_apic_id_registered(void)
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{
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return 1;
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}
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static void uv_init_apic_ldr(void)
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{
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}
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static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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int cpu = cpumask_first(cpumask);
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if ((unsigned)cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
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else
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return BAD_APICID;
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}
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static unsigned int
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uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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for_each_cpu_and(cpu, cpumask, andmask) {
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if (cpumask_test_cpu(cpu, cpu_online_mask))
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break;
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}
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return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
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}
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static unsigned int x2apic_get_apic_id(unsigned long x)
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{
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unsigned int id;
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WARN_ON(preemptible() && num_online_cpus() > 1);
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id = x | __this_cpu_read(x2apic_extra_bits);
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return id;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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unsigned long x;
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/* maskout x2apic_extra_bits ? */
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x = id;
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return x;
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}
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static unsigned int uv_read_apic_id(void)
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{
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return x2apic_get_apic_id(apic_read(APIC_ID));
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}
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static int uv_phys_pkg_id(int initial_apicid, int index_msb)
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{
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return uv_read_apic_id() >> index_msb;
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}
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static void uv_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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static int uv_probe(void)
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{
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return apic == &apic_x2apic_uv_x;
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}
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struct apic __refdata apic_x2apic_uv_x = {
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.name = "UV large system",
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.probe = uv_probe,
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.acpi_madt_oem_check = uv_acpi_madt_oem_check,
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.apic_id_registered = uv_apic_id_registered,
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.irq_delivery_mode = dest_Fixed,
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.irq_dest_mode = 0, /* physical */
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.target_cpus = uv_target_cpus,
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.disable_esr = 0,
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.dest_logical = APIC_DEST_LOGICAL,
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.check_apicid_used = NULL,
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.check_apicid_present = NULL,
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.vector_allocation_domain = uv_vector_allocation_domain,
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.init_apic_ldr = uv_init_apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.multi_timer_check = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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.apicid_to_cpu_present = NULL,
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.setup_portio_remap = NULL,
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.check_phys_apicid_present = default_check_phys_apicid_present,
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.enable_apic_mode = NULL,
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.phys_pkg_id = uv_phys_pkg_id,
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.mps_oem_check = NULL,
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.get_apic_id = x2apic_get_apic_id,
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.set_apic_id = set_apic_id,
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.apic_id_mask = 0xFFFFFFFFu,
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.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
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.cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
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.send_IPI_mask = uv_send_IPI_mask,
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.send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
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.send_IPI_allbutself = uv_send_IPI_allbutself,
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.send_IPI_all = uv_send_IPI_all,
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.send_IPI_self = uv_send_IPI_self,
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.wakeup_secondary_cpu = uv_wakeup_secondary,
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.trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
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.trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
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.wait_for_init_deassert = NULL,
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.smp_callin_clear_local_apic = NULL,
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.inquire_remote_apic = NULL,
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.read = native_apic_msr_read,
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.write = native_apic_msr_write,
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.icr_read = native_x2apic_icr_read,
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.icr_write = native_x2apic_icr_write,
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.wait_icr_idle = native_x2apic_wait_icr_idle,
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.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
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};
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static __cpuinit void set_x2apic_extra_bits(int pnode)
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{
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__this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
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}
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/*
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* Called on boot cpu.
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*/
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static __init int boot_pnode_to_blade(int pnode)
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{
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int blade;
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for (blade = 0; blade < uv_num_possible_blades(); blade++)
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if (pnode == uv_blade_info[blade].pnode)
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return blade;
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BUG();
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}
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struct redir_addr {
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unsigned long redirect;
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unsigned long alias;
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};
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#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
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static __initdata struct redir_addr redir_addrs[] = {
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
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};
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static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
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{
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union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
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union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
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int i;
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for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
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alias.v = uv_read_local_mmr(redir_addrs[i].alias);
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if (alias.s.enable && alias.s.base == 0) {
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*size = (1UL << alias.s.m_alias);
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redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
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*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
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return;
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}
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}
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*base = *size = 0;
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}
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enum map_type {map_wb, map_uc};
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static __init void map_high(char *id, unsigned long base, int pshift,
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int bshift, int max_pnode, enum map_type map_type)
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{
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unsigned long bytes, paddr;
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paddr = base << pshift;
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bytes = (1UL << bshift) * (max_pnode + 1);
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printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
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paddr + bytes);
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if (map_type == map_uc)
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init_extra_mapping_uc(paddr, bytes);
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else
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init_extra_mapping_wb(paddr, bytes);
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}
|
|
static __init void map_gru_high(int max_pnode)
|
|
{
|
|
union uvh_rh_gam_gru_overlay_config_mmr_u gru;
|
|
int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
|
|
|
|
gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
|
|
if (gru.s.enable) {
|
|
map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
|
|
gru_start_paddr = ((u64)gru.s.base << shift);
|
|
gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
|
|
|
|
}
|
|
}
|
|
|
|
static __init void map_mmr_high(int max_pnode)
|
|
{
|
|
union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
|
|
int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
|
|
|
|
mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
|
|
if (mmr.s.enable)
|
|
map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
|
|
}
|
|
|
|
static __init void map_mmioh_high(int max_pnode)
|
|
{
|
|
union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
|
|
int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
|
|
|
|
mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
|
|
if (mmioh.s.enable)
|
|
map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
|
|
max_pnode, map_uc);
|
|
}
|
|
|
|
static __init void map_low_mmrs(void)
|
|
{
|
|
init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
|
|
init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
|
|
}
|
|
|
|
static __init void uv_rtc_init(void)
|
|
{
|
|
long status;
|
|
u64 ticks_per_sec;
|
|
|
|
status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
|
|
&ticks_per_sec);
|
|
if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
|
|
printk(KERN_WARNING
|
|
"unable to determine platform RTC clock frequency, "
|
|
"guessing.\n");
|
|
/* BIOS gives wrong value for clock freq. so guess */
|
|
sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
|
|
} else
|
|
sn_rtc_cycles_per_second = ticks_per_sec;
|
|
}
|
|
|
|
/*
|
|
* percpu heartbeat timer
|
|
*/
|
|
static void uv_heartbeat(unsigned long ignored)
|
|
{
|
|
struct timer_list *timer = &uv_hub_info->scir.timer;
|
|
unsigned char bits = uv_hub_info->scir.state;
|
|
|
|
/* flip heartbeat bit */
|
|
bits ^= SCIR_CPU_HEARTBEAT;
|
|
|
|
/* is this cpu idle? */
|
|
if (idle_cpu(raw_smp_processor_id()))
|
|
bits &= ~SCIR_CPU_ACTIVITY;
|
|
else
|
|
bits |= SCIR_CPU_ACTIVITY;
|
|
|
|
/* update system controller interface reg */
|
|
uv_set_scir_bits(bits);
|
|
|
|
/* enable next timer period */
|
|
mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
|
|
}
|
|
|
|
static void __cpuinit uv_heartbeat_enable(int cpu)
|
|
{
|
|
while (!uv_cpu_hub_info(cpu)->scir.enabled) {
|
|
struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
|
|
|
|
uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
|
|
setup_timer(timer, uv_heartbeat, cpu);
|
|
timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
|
|
add_timer_on(timer, cpu);
|
|
uv_cpu_hub_info(cpu)->scir.enabled = 1;
|
|
|
|
/* also ensure that boot cpu is enabled */
|
|
cpu = 0;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
static void __cpuinit uv_heartbeat_disable(int cpu)
|
|
{
|
|
if (uv_cpu_hub_info(cpu)->scir.enabled) {
|
|
uv_cpu_hub_info(cpu)->scir.enabled = 0;
|
|
del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
|
|
}
|
|
uv_set_cpu_scir_bits(cpu, 0xff);
|
|
}
|
|
|
|
/*
|
|
* cpu hotplug notifier
|
|
*/
|
|
static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
long cpu = (long)hcpu;
|
|
|
|
switch (action) {
|
|
case CPU_ONLINE:
|
|
uv_heartbeat_enable(cpu);
|
|
break;
|
|
case CPU_DOWN_PREPARE:
|
|
uv_heartbeat_disable(cpu);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static __init void uv_scir_register_cpu_notifier(void)
|
|
{
|
|
hotcpu_notifier(uv_scir_cpu_notify, 0);
|
|
}
|
|
|
|
#else /* !CONFIG_HOTPLUG_CPU */
|
|
|
|
static __init void uv_scir_register_cpu_notifier(void)
|
|
{
|
|
}
|
|
|
|
static __init int uv_init_heartbeat(void)
|
|
{
|
|
int cpu;
|
|
|
|
if (is_uv_system())
|
|
for_each_online_cpu(cpu)
|
|
uv_heartbeat_enable(cpu);
|
|
return 0;
|
|
}
|
|
|
|
late_initcall(uv_init_heartbeat);
|
|
|
|
#endif /* !CONFIG_HOTPLUG_CPU */
|
|
|
|
/* Direct Legacy VGA I/O traffic to designated IOH */
|
|
int uv_set_vga_state(struct pci_dev *pdev, bool decode,
|
|
unsigned int command_bits, bool change_bridge)
|
|
{
|
|
int domain, bus, rc;
|
|
|
|
PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
|
|
pdev->devfn, decode, command_bits, change_bridge);
|
|
|
|
if (!change_bridge)
|
|
return 0;
|
|
|
|
if ((command_bits & PCI_COMMAND_IO) == 0)
|
|
return 0;
|
|
|
|
domain = pci_domain_nr(pdev->bus);
|
|
bus = pdev->bus->number;
|
|
|
|
rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
|
|
PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
|
|
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* Called on each cpu to initialize the per_cpu UV data area.
|
|
* FIXME: hotplug not supported yet
|
|
*/
|
|
void __cpuinit uv_cpu_init(void)
|
|
{
|
|
/* CPU 0 initilization will be done via uv_system_init. */
|
|
if (!uv_blade_info)
|
|
return;
|
|
|
|
uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
|
|
|
|
if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
|
|
set_x2apic_extra_bits(uv_hub_info->pnode);
|
|
}
|
|
|
|
/*
|
|
* When NMI is received, print a stack trace.
|
|
*/
|
|
int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
|
|
{
|
|
unsigned long real_uv_nmi;
|
|
int bid;
|
|
|
|
if (reason != DIE_NMIUNKNOWN)
|
|
return NOTIFY_OK;
|
|
|
|
if (in_crash_kexec)
|
|
/* do nothing if entering the crash kernel */
|
|
return NOTIFY_OK;
|
|
|
|
/*
|
|
* Each blade has an MMR that indicates when an NMI has been sent
|
|
* to cpus on the blade. If an NMI is detected, atomically
|
|
* clear the MMR and update a per-blade NMI count used to
|
|
* cause each cpu on the blade to notice a new NMI.
|
|
*/
|
|
bid = uv_numa_blade_id();
|
|
real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
|
|
|
|
if (unlikely(real_uv_nmi)) {
|
|
spin_lock(&uv_blade_info[bid].nmi_lock);
|
|
real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
|
|
if (real_uv_nmi) {
|
|
uv_blade_info[bid].nmi_count++;
|
|
uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK);
|
|
}
|
|
spin_unlock(&uv_blade_info[bid].nmi_lock);
|
|
}
|
|
|
|
if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count))
|
|
return NOTIFY_DONE;
|
|
|
|
__get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;
|
|
|
|
/*
|
|
* Use a lock so only one cpu prints at a time.
|
|
* This prevents intermixed output.
|
|
*/
|
|
spin_lock(&uv_nmi_lock);
|
|
pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());
|
|
dump_stack();
|
|
spin_unlock(&uv_nmi_lock);
|
|
|
|
return NOTIFY_STOP;
|
|
}
|
|
|
|
static struct notifier_block uv_dump_stack_nmi_nb = {
|
|
.notifier_call = uv_handle_nmi,
|
|
.priority = NMI_LOCAL_LOW_PRIOR - 1,
|
|
};
|
|
|
|
void uv_register_nmi_notifier(void)
|
|
{
|
|
if (register_die_notifier(&uv_dump_stack_nmi_nb))
|
|
printk(KERN_WARNING "UV NMI handler failed to register\n");
|
|
}
|
|
|
|
void uv_nmi_init(void)
|
|
{
|
|
unsigned int value;
|
|
|
|
/*
|
|
* Unmask NMI on all cpus
|
|
*/
|
|
value = apic_read(APIC_LVT1) | APIC_DM_NMI;
|
|
value &= ~APIC_LVT_MASKED;
|
|
apic_write(APIC_LVT1, value);
|
|
}
|
|
|
|
void __init uv_system_init(void)
|
|
{
|
|
union uvh_rh_gam_config_mmr_u m_n_config;
|
|
union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
|
|
union uvh_node_id_u node_id;
|
|
unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
|
|
int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
|
|
int gnode_extra, max_pnode = 0;
|
|
unsigned long mmr_base, present, paddr;
|
|
unsigned short pnode_mask, pnode_io_mask;
|
|
|
|
map_low_mmrs();
|
|
|
|
m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
|
|
m_val = m_n_config.s.m_skt;
|
|
n_val = m_n_config.s.n_skt;
|
|
mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
|
|
n_io = mmioh.s.n_io;
|
|
mmr_base =
|
|
uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
|
|
~UV_MMR_ENABLE;
|
|
pnode_mask = (1 << n_val) - 1;
|
|
pnode_io_mask = (1 << n_io) - 1;
|
|
|
|
node_id.v = uv_read_local_mmr(UVH_NODE_ID);
|
|
gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
|
|
gnode_upper = ((unsigned long)gnode_extra << m_val);
|
|
printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
|
|
n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
|
|
|
|
printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
|
|
|
|
for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
|
|
uv_possible_blades +=
|
|
hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
|
|
printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
|
|
|
|
bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
|
|
uv_blade_info = kzalloc(bytes, GFP_KERNEL);
|
|
BUG_ON(!uv_blade_info);
|
|
|
|
for (blade = 0; blade < uv_num_possible_blades(); blade++)
|
|
uv_blade_info[blade].memory_nid = -1;
|
|
|
|
get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
|
|
|
|
bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
|
|
uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
|
|
BUG_ON(!uv_node_to_blade);
|
|
memset(uv_node_to_blade, 255, bytes);
|
|
|
|
bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
|
|
uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
|
|
BUG_ON(!uv_cpu_to_blade);
|
|
memset(uv_cpu_to_blade, 255, bytes);
|
|
|
|
blade = 0;
|
|
for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
|
|
present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
|
|
for (j = 0; j < 64; j++) {
|
|
if (!test_bit(j, &present))
|
|
continue;
|
|
pnode = (i * 64 + j) & pnode_mask;
|
|
uv_blade_info[blade].pnode = pnode;
|
|
uv_blade_info[blade].nr_possible_cpus = 0;
|
|
uv_blade_info[blade].nr_online_cpus = 0;
|
|
spin_lock_init(&uv_blade_info[blade].nmi_lock);
|
|
max_pnode = max(pnode, max_pnode);
|
|
blade++;
|
|
}
|
|
}
|
|
|
|
uv_bios_init();
|
|
uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
|
|
&sn_region_size, &system_serial_number);
|
|
uv_rtc_init();
|
|
|
|
for_each_present_cpu(cpu) {
|
|
int apicid = per_cpu(x86_cpu_to_apicid, cpu);
|
|
|
|
nid = cpu_to_node(cpu);
|
|
/*
|
|
* apic_pnode_shift must be set before calling uv_apicid_to_pnode();
|
|
*/
|
|
uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
|
|
uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
|
|
pnode = uv_apicid_to_pnode(apicid);
|
|
blade = boot_pnode_to_blade(pnode);
|
|
lcpu = uv_blade_info[blade].nr_possible_cpus;
|
|
uv_blade_info[blade].nr_possible_cpus++;
|
|
|
|
/* Any node on the blade, else will contain -1. */
|
|
uv_blade_info[blade].memory_nid = nid;
|
|
|
|
uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
|
|
uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
|
|
uv_cpu_hub_info(cpu)->m_val = m_val;
|
|
uv_cpu_hub_info(cpu)->n_val = n_val;
|
|
uv_cpu_hub_info(cpu)->numa_blade_id = blade;
|
|
uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
|
|
uv_cpu_hub_info(cpu)->pnode = pnode;
|
|
uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
|
|
uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
|
|
uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
|
|
uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
|
|
uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
|
|
uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
|
|
uv_node_to_blade[nid] = blade;
|
|
uv_cpu_to_blade[cpu] = blade;
|
|
}
|
|
|
|
/* Add blade/pnode info for nodes without cpus */
|
|
for_each_online_node(nid) {
|
|
if (uv_node_to_blade[nid] >= 0)
|
|
continue;
|
|
paddr = node_start_pfn(nid) << PAGE_SHIFT;
|
|
paddr = uv_soc_phys_ram_to_gpa(paddr);
|
|
pnode = (paddr >> m_val) & pnode_mask;
|
|
blade = boot_pnode_to_blade(pnode);
|
|
uv_node_to_blade[nid] = blade;
|
|
}
|
|
|
|
map_gru_high(max_pnode);
|
|
map_mmr_high(max_pnode);
|
|
map_mmioh_high(max_pnode & pnode_io_mask);
|
|
|
|
uv_cpu_init();
|
|
uv_scir_register_cpu_notifier();
|
|
uv_register_nmi_notifier();
|
|
proc_mkdir("sgi_uv", NULL);
|
|
|
|
/* register Legacy VGA I/O redirection handler */
|
|
pci_register_set_vga_state(uv_set_vga_state);
|
|
|
|
/*
|
|
* For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
|
|
* EFI is not enabled in the kdump kernel.
|
|
*/
|
|
if (is_kdump_kernel())
|
|
reboot_type = BOOT_ACPI;
|
|
}
|
|
|
|
apic_driver(apic_x2apic_uv_x);
|