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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): released under the terms of the gnu gpl v2 0 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 9 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171439.076212120@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
366 lines
9.5 KiB
C
366 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/sh/mm/cache.c
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*
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* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
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* Copyright (C) 2002 - 2010 Paul Mundt
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/mutex.h>
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#include <linux/fs.h>
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#include <linux/smp.h>
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#include <linux/highmem.h>
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#include <linux/module.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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void (*local_flush_cache_all)(void *args) = cache_noop;
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void (*local_flush_cache_mm)(void *args) = cache_noop;
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void (*local_flush_cache_dup_mm)(void *args) = cache_noop;
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void (*local_flush_cache_page)(void *args) = cache_noop;
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void (*local_flush_cache_range)(void *args) = cache_noop;
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void (*local_flush_dcache_page)(void *args) = cache_noop;
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void (*local_flush_icache_range)(void *args) = cache_noop;
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void (*local_flush_icache_page)(void *args) = cache_noop;
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void (*local_flush_cache_sigtramp)(void *args) = cache_noop;
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void (*__flush_wback_region)(void *start, int size);
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EXPORT_SYMBOL(__flush_wback_region);
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void (*__flush_purge_region)(void *start, int size);
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EXPORT_SYMBOL(__flush_purge_region);
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void (*__flush_invalidate_region)(void *start, int size);
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EXPORT_SYMBOL(__flush_invalidate_region);
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static inline void noop__flush_region(void *start, int size)
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{
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}
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static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
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int wait)
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{
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preempt_disable();
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/* Needing IPI for cross-core flush is SHX3-specific. */
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#ifdef CONFIG_CPU_SHX3
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/*
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* It's possible that this gets called early on when IRQs are
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* still disabled due to ioremapping by the boot CPU, so don't
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* even attempt IPIs unless there are other CPUs online.
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*/
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if (num_online_cpus() > 1)
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smp_call_function(func, info, wait);
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#endif
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func(info);
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preempt_enable();
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}
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
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test_bit(PG_dcache_clean, &page->flags)) {
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void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
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memcpy(vto, src, len);
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kunmap_coherent(vto);
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} else {
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memcpy(dst, src, len);
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if (boot_cpu_data.dcache.n_aliases)
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clear_bit(PG_dcache_clean, &page->flags);
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}
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if (vma->vm_flags & VM_EXEC)
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flush_cache_page(vma, vaddr, page_to_pfn(page));
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}
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void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
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test_bit(PG_dcache_clean, &page->flags)) {
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void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
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memcpy(dst, vfrom, len);
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kunmap_coherent(vfrom);
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} else {
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memcpy(dst, src, len);
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if (boot_cpu_data.dcache.n_aliases)
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clear_bit(PG_dcache_clean, &page->flags);
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}
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}
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void copy_user_highpage(struct page *to, struct page *from,
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unsigned long vaddr, struct vm_area_struct *vma)
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{
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void *vfrom, *vto;
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vto = kmap_atomic(to);
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if (boot_cpu_data.dcache.n_aliases && page_mapcount(from) &&
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test_bit(PG_dcache_clean, &from->flags)) {
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vfrom = kmap_coherent(from, vaddr);
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copy_page(vto, vfrom);
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kunmap_coherent(vfrom);
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} else {
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vfrom = kmap_atomic(from);
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copy_page(vto, vfrom);
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kunmap_atomic(vfrom);
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}
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if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
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(vma->vm_flags & VM_EXEC))
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__flush_purge_region(vto, PAGE_SIZE);
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kunmap_atomic(vto);
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/* Make sure this page is cleared on other CPU's too before using it */
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smp_wmb();
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}
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EXPORT_SYMBOL(copy_user_highpage);
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void clear_user_highpage(struct page *page, unsigned long vaddr)
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{
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void *kaddr = kmap_atomic(page);
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clear_page(kaddr);
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if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK))
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__flush_purge_region(kaddr, PAGE_SIZE);
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kunmap_atomic(kaddr);
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}
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EXPORT_SYMBOL(clear_user_highpage);
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void __update_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t pte)
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{
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struct page *page;
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unsigned long pfn = pte_pfn(pte);
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if (!boot_cpu_data.dcache.n_aliases)
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return;
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page = pfn_to_page(pfn);
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if (pfn_valid(pfn)) {
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int dirty = !test_and_set_bit(PG_dcache_clean, &page->flags);
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if (dirty)
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__flush_purge_region(page_address(page), PAGE_SIZE);
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}
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}
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void __flush_anon_page(struct page *page, unsigned long vmaddr)
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{
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unsigned long addr = (unsigned long) page_address(page);
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if (pages_do_alias(addr, vmaddr)) {
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if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
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test_bit(PG_dcache_clean, &page->flags)) {
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void *kaddr;
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kaddr = kmap_coherent(page, vmaddr);
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/* XXX.. For now kunmap_coherent() does a purge */
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/* __flush_purge_region((void *)kaddr, PAGE_SIZE); */
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kunmap_coherent(kaddr);
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} else
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__flush_purge_region((void *)addr, PAGE_SIZE);
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}
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}
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void flush_cache_all(void)
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{
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cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
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}
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EXPORT_SYMBOL(flush_cache_all);
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void flush_cache_mm(struct mm_struct *mm)
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{
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if (boot_cpu_data.dcache.n_aliases == 0)
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return;
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cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
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}
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void flush_cache_dup_mm(struct mm_struct *mm)
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{
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if (boot_cpu_data.dcache.n_aliases == 0)
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return;
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cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
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}
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void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
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unsigned long pfn)
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{
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struct flusher_data data;
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data.vma = vma;
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data.addr1 = addr;
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data.addr2 = pfn;
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cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
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}
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct flusher_data data;
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data.vma = vma;
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data.addr1 = start;
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data.addr2 = end;
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cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
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}
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EXPORT_SYMBOL(flush_cache_range);
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void flush_dcache_page(struct page *page)
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{
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cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
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}
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EXPORT_SYMBOL(flush_dcache_page);
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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struct flusher_data data;
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data.vma = NULL;
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data.addr1 = start;
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data.addr2 = end;
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cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
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}
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EXPORT_SYMBOL(flush_icache_range);
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void flush_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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/* Nothing uses the VMA, so just pass the struct page along */
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cacheop_on_each_cpu(local_flush_icache_page, page, 1);
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}
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void flush_cache_sigtramp(unsigned long address)
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{
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cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
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}
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static void compute_alias(struct cache_info *c)
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{
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#ifdef CONFIG_MMU
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c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
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#else
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c->alias_mask = 0;
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#endif
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c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
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}
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static void __init emit_cache_params(void)
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{
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printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
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boot_cpu_data.icache.ways,
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boot_cpu_data.icache.sets,
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boot_cpu_data.icache.way_incr);
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printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
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boot_cpu_data.icache.entry_mask,
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boot_cpu_data.icache.alias_mask,
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boot_cpu_data.icache.n_aliases);
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printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
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boot_cpu_data.dcache.ways,
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boot_cpu_data.dcache.sets,
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boot_cpu_data.dcache.way_incr);
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printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
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boot_cpu_data.dcache.entry_mask,
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boot_cpu_data.dcache.alias_mask,
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boot_cpu_data.dcache.n_aliases);
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/*
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* Emit Secondary Cache parameters if the CPU has a probed L2.
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*/
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if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
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printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
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boot_cpu_data.scache.ways,
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boot_cpu_data.scache.sets,
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boot_cpu_data.scache.way_incr);
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printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
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boot_cpu_data.scache.entry_mask,
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boot_cpu_data.scache.alias_mask,
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boot_cpu_data.scache.n_aliases);
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}
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}
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void __init cpu_cache_init(void)
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{
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unsigned int cache_disabled = 0;
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#ifdef SH_CCR
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cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
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#endif
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compute_alias(&boot_cpu_data.icache);
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compute_alias(&boot_cpu_data.dcache);
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compute_alias(&boot_cpu_data.scache);
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__flush_wback_region = noop__flush_region;
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__flush_purge_region = noop__flush_region;
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__flush_invalidate_region = noop__flush_region;
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/*
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* No flushing is necessary in the disabled cache case so we can
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* just keep the noop functions in local_flush_..() and __flush_..()
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*/
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if (unlikely(cache_disabled))
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goto skip;
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if (boot_cpu_data.type == CPU_J2) {
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extern void __weak j2_cache_init(void);
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j2_cache_init();
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} else if (boot_cpu_data.family == CPU_FAMILY_SH2) {
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extern void __weak sh2_cache_init(void);
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sh2_cache_init();
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}
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if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
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extern void __weak sh2a_cache_init(void);
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sh2a_cache_init();
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}
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if (boot_cpu_data.family == CPU_FAMILY_SH3) {
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extern void __weak sh3_cache_init(void);
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sh3_cache_init();
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if ((boot_cpu_data.type == CPU_SH7705) &&
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(boot_cpu_data.dcache.sets == 512)) {
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extern void __weak sh7705_cache_init(void);
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sh7705_cache_init();
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}
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}
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if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
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(boot_cpu_data.family == CPU_FAMILY_SH4A) ||
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(boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
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extern void __weak sh4_cache_init(void);
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sh4_cache_init();
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if ((boot_cpu_data.type == CPU_SH7786) ||
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(boot_cpu_data.type == CPU_SHX3)) {
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extern void __weak shx3_cache_init(void);
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shx3_cache_init();
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}
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}
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if (boot_cpu_data.family == CPU_FAMILY_SH5) {
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extern void __weak sh5_cache_init(void);
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sh5_cache_init();
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}
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skip:
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emit_cache_params();
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}
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