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![Cao jin](/assets/img/avatar_default.png)
Commit e6401c1309
("x86/irq/64: Split the IRQ stack into its own pages")
missed to update one piece of comment as it did to its peer in Xen, which
will confuse people who still need to read comment.
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20190719081635.26528-1-caoj.fnst@cn.fujitsu.com
483 lines
13 KiB
ArmAsm
483 lines
13 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
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*
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* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
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* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
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* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
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* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
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* Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
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*/
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <linux/init.h>
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#include <asm/segment.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/msr.h>
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#include <asm/cache.h>
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#include <asm/processor-flags.h>
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#include <asm/percpu.h>
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#include <asm/nops.h>
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#include "../entry/calling.h"
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#include <asm/export.h>
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#include <asm/nospec-branch.h>
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#include <asm/fixmap.h>
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#ifdef CONFIG_PARAVIRT_XXL
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#include <asm/asm-offsets.h>
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#include <asm/paravirt.h>
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#else
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#define INTERRUPT_RETURN iretq
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#endif
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/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
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* because we need identity-mapped pages.
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*
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*/
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#define l4_index(x) (((x) >> 39) & 511)
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#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
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L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
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L4_START_KERNEL = l4_index(__START_KERNEL_map)
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L3_START_KERNEL = pud_index(__START_KERNEL_map)
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.text
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__HEAD
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.code64
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.globl startup_64
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startup_64:
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UNWIND_HINT_EMPTY
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/*
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* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
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* and someone has loaded an identity mapped page table
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* for us. These identity mapped page tables map all of the
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* kernel pages and possibly all of memory.
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*
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* %rsi holds a physical pointer to real_mode_data.
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*
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* We come here either directly from a 64bit bootloader, or from
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* arch/x86/boot/compressed/head_64.S.
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*
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* We only come here initially at boot nothing else comes here.
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*
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* Since we may be loaded at an address different from what we were
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* compiled to run at we first fixup the physical addresses in our page
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* tables and then reload them.
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*/
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/* Set up the stack for verify_cpu(), similar to initial_stack below */
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leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp
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/* Sanitize CPU configuration */
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call verify_cpu
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/*
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* Perform pagetable fixups. Additionally, if SME is active, encrypt
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* the kernel and retrieve the modifier (SME encryption mask if SME
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* is active) to be added to the initial pgdir entry that will be
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* programmed into CR3.
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*/
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leaq _text(%rip), %rdi
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pushq %rsi
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call __startup_64
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popq %rsi
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/* Form the CR3 value being sure to include the CR3 modifier */
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addq $(early_top_pgt - __START_KERNEL_map), %rax
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jmp 1f
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ENTRY(secondary_startup_64)
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UNWIND_HINT_EMPTY
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/*
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* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
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* and someone has loaded a mapped page table.
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*
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* %rsi holds a physical pointer to real_mode_data.
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*
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* We come here either from startup_64 (using physical addresses)
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* or from trampoline.S (using virtual addresses).
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*
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* Using virtual addresses from trampoline.S removes the need
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* to have any identity mapped pages in the kernel page table
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* after the boot processor executes this code.
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*/
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/* Sanitize CPU configuration */
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call verify_cpu
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/*
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* Retrieve the modifier (SME encryption mask if SME is active) to be
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* added to the initial pgdir entry that will be programmed into CR3.
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*/
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pushq %rsi
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call __startup_secondary_64
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popq %rsi
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/* Form the CR3 value being sure to include the CR3 modifier */
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addq $(init_top_pgt - __START_KERNEL_map), %rax
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1:
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/* Enable PAE mode, PGE and LA57 */
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movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
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#ifdef CONFIG_X86_5LEVEL
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testl $1, __pgtable_l5_enabled(%rip)
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jz 1f
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orl $X86_CR4_LA57, %ecx
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1:
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#endif
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movq %rcx, %cr4
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/* Setup early boot stage 4-/5-level pagetables. */
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addq phys_base(%rip), %rax
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movq %rax, %cr3
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/* Ensure I am executing from virtual addresses */
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movq $1f, %rax
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ANNOTATE_RETPOLINE_SAFE
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jmp *%rax
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1:
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UNWIND_HINT_EMPTY
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/* Check if nx is implemented */
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movl $0x80000001, %eax
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cpuid
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movl %edx,%edi
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/* Setup EFER (Extended Feature Enable Register) */
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_SCE, %eax /* Enable System Call */
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btl $20,%edi /* No Execute supported? */
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jnc 1f
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btsl $_EFER_NX, %eax
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btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
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1: wrmsr /* Make changes effective */
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/* Setup cr0 */
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movl $CR0_STATE, %eax
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/* Make changes effective */
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movq %rax, %cr0
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/* Setup a boot time stack */
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movq initial_stack(%rip), %rsp
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/* zero EFLAGS after setting rsp */
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pushq $0
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popfq
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/*
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* We must switch to a new descriptor in kernel space for the GDT
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* because soon the kernel won't have access anymore to the userspace
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* addresses where we're currently running on. We have to do that here
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* because in 32bit we couldn't load a 64bit linear address.
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*/
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lgdt early_gdt_descr(%rip)
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/* set up data segments */
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xorl %eax,%eax
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movl %eax,%ds
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movl %eax,%ss
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movl %eax,%es
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/*
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* We don't really need to load %fs or %gs, but load them anyway
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* to kill any stale realmode selectors. This allows execution
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* under VT hardware.
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*/
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movl %eax,%fs
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movl %eax,%gs
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/* Set up %gs.
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*
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* The base of %gs always points to fixed_percpu_data. If the
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* stack protector canary is enabled, it is located at %gs:40.
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* Note that, on SMP, the boot cpu uses init data section until
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* the per cpu areas are set up.
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*/
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movl $MSR_GS_BASE,%ecx
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movl initial_gs(%rip),%eax
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movl initial_gs+4(%rip),%edx
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wrmsr
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/* rsi is pointer to real mode structure with interesting info.
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pass it to C */
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movq %rsi, %rdi
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.Ljump_to_C_code:
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/*
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* Jump to run C code and to be on a real kernel address.
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* Since we are running on identity-mapped space we have to jump
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* to the full 64bit address, this is only possible as indirect
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* jump. In addition we need to ensure %cs is set so we make this
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* a far return.
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*
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* Note: do not change to far jump indirect with 64bit offset.
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*
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* AMD does not support far jump indirect with 64bit offset.
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* AMD64 Architecture Programmer's Manual, Volume 3: states only
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* JMP FAR mem16:16 FF /5 Far jump indirect,
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* with the target specified by a far pointer in memory.
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* JMP FAR mem16:32 FF /5 Far jump indirect,
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* with the target specified by a far pointer in memory.
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*
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* Intel64 does support 64bit offset.
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* Software Developer Manual Vol 2: states:
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* FF /5 JMP m16:16 Jump far, absolute indirect,
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* address given in m16:16
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* FF /5 JMP m16:32 Jump far, absolute indirect,
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* address given in m16:32.
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* REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
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* address given in m16:64.
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*/
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pushq $.Lafter_lret # put return address on stack for unwinder
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xorl %ebp, %ebp # clear frame pointer
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movq initial_code(%rip), %rax
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pushq $__KERNEL_CS # set correct cs
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pushq %rax # target address in negative space
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lretq
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.Lafter_lret:
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END(secondary_startup_64)
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#include "verify_cpu.S"
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#ifdef CONFIG_HOTPLUG_CPU
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/*
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* Boot CPU0 entry point. It's called from play_dead(). Everything has been set
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* up already except stack. We just set up stack here. Then call
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* start_secondary() via .Ljump_to_C_code.
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*/
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ENTRY(start_cpu0)
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UNWIND_HINT_EMPTY
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movq initial_stack(%rip), %rsp
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jmp .Ljump_to_C_code
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END(start_cpu0)
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#endif
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/* Both SMP bootup and ACPI suspend change these variables */
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__REFDATA
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.balign 8
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GLOBAL(initial_code)
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.quad x86_64_start_kernel
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GLOBAL(initial_gs)
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.quad INIT_PER_CPU_VAR(fixed_percpu_data)
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GLOBAL(initial_stack)
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/*
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* The SIZEOF_PTREGS gap is a convention which helps the in-kernel
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* unwinder reliably detect the end of the stack.
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*/
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.quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS
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__FINITDATA
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__INIT
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ENTRY(early_idt_handler_array)
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i = 0
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.rept NUM_EXCEPTION_VECTORS
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.if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
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UNWIND_HINT_IRET_REGS
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pushq $0 # Dummy error code, to make stack frame uniform
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.else
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UNWIND_HINT_IRET_REGS offset=8
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.endif
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pushq $i # 72(%rsp) Vector number
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jmp early_idt_handler_common
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UNWIND_HINT_IRET_REGS
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i = i + 1
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.fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
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.endr
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UNWIND_HINT_IRET_REGS offset=16
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END(early_idt_handler_array)
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early_idt_handler_common:
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/*
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* The stack is the hardware frame, an error code or zero, and the
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* vector number.
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*/
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cld
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incl early_recursion_flag(%rip)
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/* The vector number is currently in the pt_regs->di slot. */
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pushq %rsi /* pt_regs->si */
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movq 8(%rsp), %rsi /* RSI = vector number */
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movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
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pushq %rdx /* pt_regs->dx */
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pushq %rcx /* pt_regs->cx */
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pushq %rax /* pt_regs->ax */
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pushq %r8 /* pt_regs->r8 */
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pushq %r9 /* pt_regs->r9 */
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pushq %r10 /* pt_regs->r10 */
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pushq %r11 /* pt_regs->r11 */
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pushq %rbx /* pt_regs->bx */
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pushq %rbp /* pt_regs->bp */
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pushq %r12 /* pt_regs->r12 */
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pushq %r13 /* pt_regs->r13 */
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pushq %r14 /* pt_regs->r14 */
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pushq %r15 /* pt_regs->r15 */
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UNWIND_HINT_REGS
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cmpq $14,%rsi /* Page fault? */
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jnz 10f
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GET_CR2_INTO(%rdi) /* can clobber %rax if pv */
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call early_make_pgtable
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andl %eax,%eax
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jz 20f /* All good */
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10:
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movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
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call early_fixup_exception
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20:
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decl early_recursion_flag(%rip)
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jmp restore_regs_and_return_to_kernel
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END(early_idt_handler_common)
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__INITDATA
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.balign 4
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GLOBAL(early_recursion_flag)
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.long 0
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#define NEXT_PAGE(name) \
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.balign PAGE_SIZE; \
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GLOBAL(name)
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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/*
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* Each PGD needs to be 8k long and 8k aligned. We do not
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* ever go out to userspace with these, so we do not
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* strictly *need* the second page, but this allows us to
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* have a single set_pgd() implementation that does not
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* need to worry about whether it has 4k or 8k to work
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* with.
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*
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* This ensures PGDs are 8k long:
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*/
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#define PTI_USER_PGD_FILL 512
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/* This ensures they are 8k-aligned: */
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#define NEXT_PGD_PAGE(name) \
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.balign 2 * PAGE_SIZE; \
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GLOBAL(name)
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#else
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#define NEXT_PGD_PAGE(name) NEXT_PAGE(name)
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#define PTI_USER_PGD_FILL 0
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#endif
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/* Automate the creation of 1 to 1 mapping pmd entries */
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#define PMDS(START, PERM, COUNT) \
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i = 0 ; \
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.rept (COUNT) ; \
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.quad (START) + (i << PMD_SHIFT) + (PERM) ; \
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i = i + 1 ; \
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.endr
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__INITDATA
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NEXT_PGD_PAGE(early_top_pgt)
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.fill 512,8,0
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.fill PTI_USER_PGD_FILL,8,0
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NEXT_PAGE(early_dynamic_pgts)
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.fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
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.data
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#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
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NEXT_PGD_PAGE(init_top_pgt)
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.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
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.org init_top_pgt + L4_PAGE_OFFSET*8, 0
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.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
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.org init_top_pgt + L4_START_KERNEL*8, 0
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/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
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.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
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.fill PTI_USER_PGD_FILL,8,0
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NEXT_PAGE(level3_ident_pgt)
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.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
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.fill 511, 8, 0
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NEXT_PAGE(level2_ident_pgt)
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/*
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* Since I easily can, map the first 1G.
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* Don't set NX because code runs from these pages.
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*
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* Note: This sets _PAGE_GLOBAL despite whether
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* the CPU supports it or it is enabled. But,
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* the CPU should ignore the bit.
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*/
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PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
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#else
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NEXT_PGD_PAGE(init_top_pgt)
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.fill 512,8,0
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.fill PTI_USER_PGD_FILL,8,0
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#endif
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#ifdef CONFIG_X86_5LEVEL
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NEXT_PAGE(level4_kernel_pgt)
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.fill 511,8,0
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.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
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#endif
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NEXT_PAGE(level3_kernel_pgt)
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.fill L3_START_KERNEL,8,0
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/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
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.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
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.quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
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NEXT_PAGE(level2_kernel_pgt)
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/*
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* 512 MB kernel mapping. We spend a full page on this pagetable
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* anyway.
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*
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* The kernel code+data+bss must not be bigger than that.
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*
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* (NOTE: at +512MB starts the module area, see MODULES_VADDR.
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* If you want to increase this then increase MODULES_VADDR
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* too.)
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*
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* This table is eventually used by the kernel during normal
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* runtime. Care must be taken to clear out undesired bits
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* later, like _PAGE_RW or _PAGE_GLOBAL in some cases.
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*/
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PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
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KERNEL_IMAGE_SIZE/PMD_SIZE)
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NEXT_PAGE(level2_fixmap_pgt)
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.fill (512 - 4 - FIXMAP_PMD_NUM),8,0
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pgtno = 0
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.rept (FIXMAP_PMD_NUM)
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.quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
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+ _PAGE_TABLE_NOENC;
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pgtno = pgtno + 1
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.endr
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/* 6 MB reserved space + a 2MB hole */
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.fill 4,8,0
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NEXT_PAGE(level1_fixmap_pgt)
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.rept (FIXMAP_PMD_NUM)
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.fill 512,8,0
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.endr
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#undef PMDS
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.data
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.align 16
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.globl early_gdt_descr
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early_gdt_descr:
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.word GDT_ENTRIES*8-1
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early_gdt_descr_base:
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.quad INIT_PER_CPU_VAR(gdt_page)
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ENTRY(phys_base)
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/* This must match the first entry in level2_kernel_pgt */
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.quad 0x0000000000000000
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EXPORT_SYMBOL(phys_base)
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#include "../../x86/xen/xen-head.S"
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__PAGE_ALIGNED_BSS
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NEXT_PAGE(empty_zero_page)
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.skip PAGE_SIZE
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EXPORT_SYMBOL(empty_zero_page)
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|