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![Peter Zijlstra](/assets/img/avatar_default.png)
Despite the current efforts to read CR2 before tracing happens there still exist a number of possible holes: idtentry page_fault do_page_fault has_error_code=1 call error_entry TRACE_IRQS_OFF call trace_hardirqs_off* #PF // modifies CR2 CALL_enter_from_user_mode __context_tracking_exit() trace_user_exit(0) #PF // modifies CR2 call do_page_fault address = read_cr2(); /* whoopsie */ And similar for i386. Fix it by pulling the CR2 read into the entry code, before any of that stuff gets a chance to run and ruin things. Reported-by: He Zhe <zhe.he@windriver.com> Reported-by: Eiichi Tsukata <devel@etsukata.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andy Lutomirski <luto@kernel.org> Cc: bp@alien8.de Cc: rostedt@goodmis.org Cc: torvalds@linux-foundation.org Cc: hpa@zytor.com Cc: dave.hansen@linux.intel.com Cc: jgross@suse.com Cc: joel@joelfernandes.org Link: https://lkml.kernel.org/r/20190711114336.116812491@infradead.org Debugged-by: Steven Rostedt <rostedt@goodmis.org>
951 lines
27 KiB
C
951 lines
27 KiB
C
/*
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* Copyright (C) 1991, 1992 Linus Torvalds
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* Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
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*
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* Pentium III FXSR, SSE support
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* Gareth Hughes <gareth@valinux.com>, May 2000
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*/
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/*
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* Handle hardware traps and faults.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/context_tracking.h>
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#include <linux/interrupt.h>
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#include <linux/kallsyms.h>
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#include <linux/spinlock.h>
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#include <linux/kprobes.h>
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#include <linux/uaccess.h>
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#include <linux/kdebug.h>
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#include <linux/kgdb.h>
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/ptrace.h>
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#include <linux/uprobes.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/kexec.h>
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#include <linux/sched.h>
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#include <linux/sched/task_stack.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/bug.h>
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#include <linux/nmi.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#if defined(CONFIG_EDAC)
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#include <linux/edac.h>
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#endif
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#include <asm/stacktrace.h>
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#include <asm/processor.h>
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#include <asm/debugreg.h>
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#include <linux/atomic.h>
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#include <asm/text-patching.h>
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#include <asm/ftrace.h>
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#include <asm/traps.h>
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#include <asm/desc.h>
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#include <asm/fpu/internal.h>
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#include <asm/cpu_entry_area.h>
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#include <asm/mce.h>
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#include <asm/fixmap.h>
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#include <asm/mach_traps.h>
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#include <asm/alternative.h>
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#include <asm/fpu/xstate.h>
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#include <asm/trace/mpx.h>
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#include <asm/mpx.h>
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#include <asm/vm86.h>
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#include <asm/umip.h>
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#ifdef CONFIG_X86_64
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#include <asm/x86_init.h>
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#include <asm/pgalloc.h>
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#include <asm/proto.h>
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#else
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#include <asm/processor-flags.h>
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#include <asm/setup.h>
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#include <asm/proto.h>
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#endif
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DECLARE_BITMAP(system_vectors, NR_VECTORS);
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static inline void cond_local_irq_enable(struct pt_regs *regs)
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{
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if (regs->flags & X86_EFLAGS_IF)
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local_irq_enable();
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}
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static inline void cond_local_irq_disable(struct pt_regs *regs)
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{
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if (regs->flags & X86_EFLAGS_IF)
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local_irq_disable();
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}
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/*
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* In IST context, we explicitly disable preemption. This serves two
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* purposes: it makes it much less likely that we would accidentally
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* schedule in IST context and it will force a warning if we somehow
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* manage to schedule by accident.
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*/
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void ist_enter(struct pt_regs *regs)
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{
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if (user_mode(regs)) {
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RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
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} else {
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/*
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* We might have interrupted pretty much anything. In
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* fact, if we're a machine check, we can even interrupt
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* NMI processing. We don't want in_nmi() to return true,
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* but we need to notify RCU.
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*/
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rcu_nmi_enter();
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}
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preempt_disable();
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/* This code is a bit fragile. Test it. */
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RCU_LOCKDEP_WARN(!rcu_is_watching(), "ist_enter didn't work");
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}
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NOKPROBE_SYMBOL(ist_enter);
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void ist_exit(struct pt_regs *regs)
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{
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preempt_enable_no_resched();
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if (!user_mode(regs))
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rcu_nmi_exit();
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}
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/**
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* ist_begin_non_atomic() - begin a non-atomic section in an IST exception
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* @regs: regs passed to the IST exception handler
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*
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* IST exception handlers normally cannot schedule. As a special
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* exception, if the exception interrupted userspace code (i.e.
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* user_mode(regs) would return true) and the exception was not
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* a double fault, it can be safe to schedule. ist_begin_non_atomic()
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* begins a non-atomic section within an ist_enter()/ist_exit() region.
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* Callers are responsible for enabling interrupts themselves inside
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* the non-atomic section, and callers must call ist_end_non_atomic()
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* before ist_exit().
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*/
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void ist_begin_non_atomic(struct pt_regs *regs)
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{
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BUG_ON(!user_mode(regs));
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/*
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* Sanity check: we need to be on the normal thread stack. This
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* will catch asm bugs and any attempt to use ist_preempt_enable
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* from double_fault.
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*/
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BUG_ON(!on_thread_stack());
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preempt_enable_no_resched();
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}
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/**
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* ist_end_non_atomic() - begin a non-atomic section in an IST exception
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*
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* Ends a non-atomic section started with ist_begin_non_atomic().
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*/
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void ist_end_non_atomic(void)
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{
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preempt_disable();
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}
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int is_valid_bugaddr(unsigned long addr)
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{
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unsigned short ud;
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if (addr < TASK_SIZE_MAX)
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return 0;
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if (probe_kernel_address((unsigned short *)addr, ud))
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return 0;
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return ud == INSN_UD0 || ud == INSN_UD2;
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}
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int fixup_bug(struct pt_regs *regs, int trapnr)
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{
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if (trapnr != X86_TRAP_UD)
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return 0;
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switch (report_bug(regs->ip, regs)) {
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case BUG_TRAP_TYPE_NONE:
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case BUG_TRAP_TYPE_BUG:
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break;
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case BUG_TRAP_TYPE_WARN:
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regs->ip += LEN_UD2;
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return 1;
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}
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return 0;
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}
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static nokprobe_inline int
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do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
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struct pt_regs *regs, long error_code)
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{
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if (v8086_mode(regs)) {
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/*
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* Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
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* On nmi (interrupt 2), do_trap should not be called.
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*/
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if (trapnr < X86_TRAP_UD) {
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if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
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error_code, trapnr))
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return 0;
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}
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} else if (!user_mode(regs)) {
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if (fixup_exception(regs, trapnr, error_code, 0))
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return 0;
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tsk->thread.error_code = error_code;
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tsk->thread.trap_nr = trapnr;
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die(str, regs, error_code);
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}
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/*
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* We want error_code and trap_nr set for userspace faults and
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* kernelspace faults which result in die(), but not
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* kernelspace faults which are fixed up. die() gives the
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* process no chance to handle the signal and notice the
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* kernel fault information, so that won't result in polluting
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* the information about previously queued, but not yet
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* delivered, faults. See also do_general_protection below.
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*/
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tsk->thread.error_code = error_code;
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tsk->thread.trap_nr = trapnr;
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return -1;
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}
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static void show_signal(struct task_struct *tsk, int signr,
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const char *type, const char *desc,
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struct pt_regs *regs, long error_code)
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{
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if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
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printk_ratelimit()) {
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pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
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tsk->comm, task_pid_nr(tsk), type, desc,
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regs->ip, regs->sp, error_code);
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print_vma_addr(KERN_CONT " in ", regs->ip);
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pr_cont("\n");
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}
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}
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static void
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do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
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long error_code, int sicode, void __user *addr)
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{
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struct task_struct *tsk = current;
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if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
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return;
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show_signal(tsk, signr, "trap ", str, regs, error_code);
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if (!sicode)
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force_sig(signr);
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else
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force_sig_fault(signr, sicode, addr);
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}
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NOKPROBE_SYMBOL(do_trap);
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static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
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unsigned long trapnr, int signr, int sicode, void __user *addr)
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{
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RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
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/*
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* WARN*()s end up here; fix them up before we call the
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* notifier chain.
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*/
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if (!user_mode(regs) && fixup_bug(regs, trapnr))
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return;
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if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
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NOTIFY_STOP) {
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cond_local_irq_enable(regs);
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do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
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}
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}
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#define IP ((void __user *)uprobe_get_trap_addr(regs))
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#define DO_ERROR(trapnr, signr, sicode, addr, str, name) \
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dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \
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{ \
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do_error_trap(regs, error_code, str, trapnr, signr, sicode, addr); \
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}
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DO_ERROR(X86_TRAP_DE, SIGFPE, FPE_INTDIV, IP, "divide error", divide_error)
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DO_ERROR(X86_TRAP_OF, SIGSEGV, 0, NULL, "overflow", overflow)
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DO_ERROR(X86_TRAP_UD, SIGILL, ILL_ILLOPN, IP, "invalid opcode", invalid_op)
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DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, 0, NULL, "coprocessor segment overrun", coprocessor_segment_overrun)
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DO_ERROR(X86_TRAP_TS, SIGSEGV, 0, NULL, "invalid TSS", invalid_TSS)
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DO_ERROR(X86_TRAP_NP, SIGBUS, 0, NULL, "segment not present", segment_not_present)
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DO_ERROR(X86_TRAP_SS, SIGBUS, 0, NULL, "stack segment", stack_segment)
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DO_ERROR(X86_TRAP_AC, SIGBUS, BUS_ADRALN, NULL, "alignment check", alignment_check)
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#undef IP
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#ifdef CONFIG_VMAP_STACK
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__visible void __noreturn handle_stack_overflow(const char *message,
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struct pt_regs *regs,
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unsigned long fault_address)
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{
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printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n",
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(void *)fault_address, current->stack,
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(char *)current->stack + THREAD_SIZE - 1);
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die(message, regs, 0);
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/* Be absolutely certain we don't return. */
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panic("%s", message);
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}
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#endif
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#ifdef CONFIG_X86_64
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/* Runs on IST stack */
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dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code, unsigned long cr2)
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{
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static const char str[] = "double fault";
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struct task_struct *tsk = current;
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#ifdef CONFIG_X86_ESPFIX64
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extern unsigned char native_irq_return_iret[];
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/*
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* If IRET takes a non-IST fault on the espfix64 stack, then we
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* end up promoting it to a doublefault. In that case, take
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* advantage of the fact that we're not using the normal (TSS.sp0)
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* stack right now. We can write a fake #GP(0) frame at TSS.sp0
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* and then modify our own IRET frame so that, when we return,
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* we land directly at the #GP(0) vector with the stack already
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* set up according to its expectations.
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*
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* The net result is that our #GP handler will think that we
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* entered from usermode with the bad user context.
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*
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* No need for ist_enter here because we don't use RCU.
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*/
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if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
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regs->cs == __KERNEL_CS &&
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regs->ip == (unsigned long)native_irq_return_iret)
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{
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struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
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/*
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* regs->sp points to the failing IRET frame on the
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* ESPFIX64 stack. Copy it to the entry stack. This fills
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* in gpregs->ss through gpregs->ip.
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*
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*/
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memmove(&gpregs->ip, (void *)regs->sp, 5*8);
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gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
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/*
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* Adjust our frame so that we return straight to the #GP
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* vector with the expected RSP value. This is safe because
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* we won't enable interupts or schedule before we invoke
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* general_protection, so nothing will clobber the stack
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* frame we just set up.
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*
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* We will enter general_protection with kernel GSBASE,
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* which is what the stub expects, given that the faulting
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* RIP will be the IRET instruction.
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*/
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regs->ip = (unsigned long)general_protection;
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regs->sp = (unsigned long)&gpregs->orig_ax;
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return;
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}
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#endif
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ist_enter(regs);
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notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
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tsk->thread.error_code = error_code;
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tsk->thread.trap_nr = X86_TRAP_DF;
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#ifdef CONFIG_VMAP_STACK
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/*
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* If we overflow the stack into a guard page, the CPU will fail
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* to deliver #PF and will send #DF instead. Similarly, if we
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* take any non-IST exception while too close to the bottom of
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* the stack, the processor will get a page fault while
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* delivering the exception and will generate a double fault.
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*
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* According to the SDM (footnote in 6.15 under "Interrupt 14 -
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* Page-Fault Exception (#PF):
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*
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* Processors update CR2 whenever a page fault is detected. If a
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* second page fault occurs while an earlier page fault is being
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* delivered, the faulting linear address of the second fault will
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* overwrite the contents of CR2 (replacing the previous
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* address). These updates to CR2 occur even if the page fault
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* results in a double fault or occurs during the delivery of a
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* double fault.
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*
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* The logic below has a small possibility of incorrectly diagnosing
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* some errors as stack overflows. For example, if the IDT or GDT
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* gets corrupted such that #GP delivery fails due to a bad descriptor
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* causing #GP and we hit this condition while CR2 coincidentally
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* points to the stack guard page, we'll think we overflowed the
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* stack. Given that we're going to panic one way or another
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* if this happens, this isn't necessarily worth fixing.
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*
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* If necessary, we could improve the test by only diagnosing
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* a stack overflow if the saved RSP points within 47 bytes of
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* the bottom of the stack: if RSP == tsk_stack + 48 and we
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* take an exception, the stack is already aligned and there
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* will be enough room SS, RSP, RFLAGS, CS, RIP, and a
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* possible error code, so a stack overflow would *not* double
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* fault. With any less space left, exception delivery could
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* fail, and, as a practical matter, we've overflowed the
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* stack even if the actual trigger for the double fault was
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* something else.
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*/
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if ((unsigned long)task_stack_page(tsk) - 1 - cr2 < PAGE_SIZE)
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handle_stack_overflow("kernel stack overflow (double-fault)", regs, cr2);
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#endif
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#ifdef CONFIG_DOUBLEFAULT
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df_debug(regs, error_code);
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#endif
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/*
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* This is always a kernel trap and never fixable (and thus must
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* never return).
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*/
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for (;;)
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die(str, regs, error_code);
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}
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#endif
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dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
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{
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const struct mpx_bndcsr *bndcsr;
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RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
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if (notify_die(DIE_TRAP, "bounds", regs, error_code,
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X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
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return;
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cond_local_irq_enable(regs);
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if (!user_mode(regs))
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die("bounds", regs, error_code);
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if (!cpu_feature_enabled(X86_FEATURE_MPX)) {
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/* The exception is not from Intel MPX */
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goto exit_trap;
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}
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/*
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* We need to look at BNDSTATUS to resolve this exception.
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* A NULL here might mean that it is in its 'init state',
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* which is all zeros which indicates MPX was not
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* responsible for the exception.
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*/
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bndcsr = get_xsave_field_ptr(XFEATURE_BNDCSR);
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if (!bndcsr)
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goto exit_trap;
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|
trace_bounds_exception_mpx(bndcsr);
|
|
/*
|
|
* The error code field of the BNDSTATUS register communicates status
|
|
* information of a bound range exception #BR or operation involving
|
|
* bound directory.
|
|
*/
|
|
switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) {
|
|
case 2: /* Bound directory has invalid entry. */
|
|
if (mpx_handle_bd_fault())
|
|
goto exit_trap;
|
|
break; /* Success, it was handled */
|
|
case 1: /* Bound violation. */
|
|
{
|
|
struct task_struct *tsk = current;
|
|
struct mpx_fault_info mpx;
|
|
|
|
if (mpx_fault_info(&mpx, regs)) {
|
|
/*
|
|
* We failed to decode the MPX instruction. Act as if
|
|
* the exception was not caused by MPX.
|
|
*/
|
|
goto exit_trap;
|
|
}
|
|
/*
|
|
* Success, we decoded the instruction and retrieved
|
|
* an 'mpx' containing the address being accessed
|
|
* which caused the exception. This information
|
|
* allows and application to possibly handle the
|
|
* #BR exception itself.
|
|
*/
|
|
if (!do_trap_no_signal(tsk, X86_TRAP_BR, "bounds", regs,
|
|
error_code))
|
|
break;
|
|
|
|
show_signal(tsk, SIGSEGV, "trap ", "bounds", regs, error_code);
|
|
|
|
force_sig_bnderr(mpx.addr, mpx.lower, mpx.upper);
|
|
break;
|
|
}
|
|
case 0: /* No exception caused by Intel MPX operations. */
|
|
goto exit_trap;
|
|
default:
|
|
die("bounds", regs, error_code);
|
|
}
|
|
|
|
return;
|
|
|
|
exit_trap:
|
|
/*
|
|
* This path out is for all the cases where we could not
|
|
* handle the exception in some way (like allocating a
|
|
* table or telling userspace about it. We will also end
|
|
* up here if the kernel has MPX turned off at compile
|
|
* time..
|
|
*/
|
|
do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, 0, NULL);
|
|
}
|
|
|
|
dotraplinkage void
|
|
do_general_protection(struct pt_regs *regs, long error_code)
|
|
{
|
|
const char *desc = "general protection fault";
|
|
struct task_struct *tsk;
|
|
|
|
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
|
|
cond_local_irq_enable(regs);
|
|
|
|
if (static_cpu_has(X86_FEATURE_UMIP)) {
|
|
if (user_mode(regs) && fixup_umip_exception(regs))
|
|
return;
|
|
}
|
|
|
|
if (v8086_mode(regs)) {
|
|
local_irq_enable();
|
|
handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
|
|
return;
|
|
}
|
|
|
|
tsk = current;
|
|
if (!user_mode(regs)) {
|
|
if (fixup_exception(regs, X86_TRAP_GP, error_code, 0))
|
|
return;
|
|
|
|
tsk->thread.error_code = error_code;
|
|
tsk->thread.trap_nr = X86_TRAP_GP;
|
|
|
|
/*
|
|
* To be potentially processing a kprobe fault and to
|
|
* trust the result from kprobe_running(), we have to
|
|
* be non-preemptible.
|
|
*/
|
|
if (!preemptible() && kprobe_running() &&
|
|
kprobe_fault_handler(regs, X86_TRAP_GP))
|
|
return;
|
|
|
|
if (notify_die(DIE_GPF, desc, regs, error_code,
|
|
X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP)
|
|
die(desc, regs, error_code);
|
|
return;
|
|
}
|
|
|
|
tsk->thread.error_code = error_code;
|
|
tsk->thread.trap_nr = X86_TRAP_GP;
|
|
|
|
show_signal(tsk, SIGSEGV, "", desc, regs, error_code);
|
|
|
|
force_sig(SIGSEGV);
|
|
}
|
|
NOKPROBE_SYMBOL(do_general_protection);
|
|
|
|
dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
|
|
{
|
|
#ifdef CONFIG_DYNAMIC_FTRACE
|
|
/*
|
|
* ftrace must be first, everything else may cause a recursive crash.
|
|
* See note by declaration of modifying_ftrace_code in ftrace.c
|
|
*/
|
|
if (unlikely(atomic_read(&modifying_ftrace_code)) &&
|
|
ftrace_int3_handler(regs))
|
|
return;
|
|
#endif
|
|
if (poke_int3_handler(regs))
|
|
return;
|
|
|
|
/*
|
|
* Use ist_enter despite the fact that we don't use an IST stack.
|
|
* We can be called from a kprobe in non-CONTEXT_KERNEL kernel
|
|
* mode or even during context tracking state changes.
|
|
*
|
|
* This means that we can't schedule. That's okay.
|
|
*/
|
|
ist_enter(regs);
|
|
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
|
|
#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
|
|
if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
|
|
SIGTRAP) == NOTIFY_STOP)
|
|
goto exit;
|
|
#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
|
|
|
|
#ifdef CONFIG_KPROBES
|
|
if (kprobe_int3_handler(regs))
|
|
goto exit;
|
|
#endif
|
|
|
|
if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
|
|
SIGTRAP) == NOTIFY_STOP)
|
|
goto exit;
|
|
|
|
cond_local_irq_enable(regs);
|
|
do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, 0, NULL);
|
|
cond_local_irq_disable(regs);
|
|
|
|
exit:
|
|
ist_exit(regs);
|
|
}
|
|
NOKPROBE_SYMBOL(do_int3);
|
|
|
|
#ifdef CONFIG_X86_64
|
|
/*
|
|
* Help handler running on a per-cpu (IST or entry trampoline) stack
|
|
* to switch to the normal thread stack if the interrupted code was in
|
|
* user mode. The actual stack switch is done in entry_64.S
|
|
*/
|
|
asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs)
|
|
{
|
|
struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1;
|
|
if (regs != eregs)
|
|
*regs = *eregs;
|
|
return regs;
|
|
}
|
|
NOKPROBE_SYMBOL(sync_regs);
|
|
|
|
struct bad_iret_stack {
|
|
void *error_entry_ret;
|
|
struct pt_regs regs;
|
|
};
|
|
|
|
asmlinkage __visible notrace
|
|
struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
|
|
{
|
|
/*
|
|
* This is called from entry_64.S early in handling a fault
|
|
* caused by a bad iret to user mode. To handle the fault
|
|
* correctly, we want to move our stack frame to where it would
|
|
* be had we entered directly on the entry stack (rather than
|
|
* just below the IRET frame) and we want to pretend that the
|
|
* exception came from the IRET target.
|
|
*/
|
|
struct bad_iret_stack *new_stack =
|
|
(struct bad_iret_stack *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
|
|
|
|
/* Copy the IRET target to the new stack. */
|
|
memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8);
|
|
|
|
/* Copy the remainder of the stack from the current stack. */
|
|
memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip));
|
|
|
|
BUG_ON(!user_mode(&new_stack->regs));
|
|
return new_stack;
|
|
}
|
|
NOKPROBE_SYMBOL(fixup_bad_iret);
|
|
#endif
|
|
|
|
static bool is_sysenter_singlestep(struct pt_regs *regs)
|
|
{
|
|
/*
|
|
* We don't try for precision here. If we're anywhere in the region of
|
|
* code that can be single-stepped in the SYSENTER entry path, then
|
|
* assume that this is a useless single-step trap due to SYSENTER
|
|
* being invoked with TF set. (We don't know in advance exactly
|
|
* which instructions will be hit because BTF could plausibly
|
|
* be set.)
|
|
*/
|
|
#ifdef CONFIG_X86_32
|
|
return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
|
|
(unsigned long)__end_SYSENTER_singlestep_region -
|
|
(unsigned long)__begin_SYSENTER_singlestep_region;
|
|
#elif defined(CONFIG_IA32_EMULATION)
|
|
return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
|
|
(unsigned long)__end_entry_SYSENTER_compat -
|
|
(unsigned long)entry_SYSENTER_compat;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Our handling of the processor debug registers is non-trivial.
|
|
* We do not clear them on entry and exit from the kernel. Therefore
|
|
* it is possible to get a watchpoint trap here from inside the kernel.
|
|
* However, the code in ./ptrace.c has ensured that the user can
|
|
* only set watchpoints on userspace addresses. Therefore the in-kernel
|
|
* watchpoint trap can only occur in code which is reading/writing
|
|
* from user space. Such code must not hold kernel locks (since it
|
|
* can equally take a page fault), therefore it is safe to call
|
|
* force_sig_info even though that claims and releases locks.
|
|
*
|
|
* Code in ./signal.c ensures that the debug control register
|
|
* is restored before we deliver any signal, and therefore that
|
|
* user code runs with the correct debug control register even though
|
|
* we clear it here.
|
|
*
|
|
* Being careful here means that we don't have to be as careful in a
|
|
* lot of more complicated places (task switching can be a bit lazy
|
|
* about restoring all the debug state, and ptrace doesn't have to
|
|
* find every occurrence of the TF bit that could be saved away even
|
|
* by user code)
|
|
*
|
|
* May run on IST stack.
|
|
*/
|
|
dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
|
|
{
|
|
struct task_struct *tsk = current;
|
|
int user_icebp = 0;
|
|
unsigned long dr6;
|
|
int si_code;
|
|
|
|
ist_enter(regs);
|
|
|
|
get_debugreg(dr6, 6);
|
|
/*
|
|
* The Intel SDM says:
|
|
*
|
|
* Certain debug exceptions may clear bits 0-3. The remaining
|
|
* contents of the DR6 register are never cleared by the
|
|
* processor. To avoid confusion in identifying debug
|
|
* exceptions, debug handlers should clear the register before
|
|
* returning to the interrupted task.
|
|
*
|
|
* Keep it simple: clear DR6 immediately.
|
|
*/
|
|
set_debugreg(0, 6);
|
|
|
|
/* Filter out all the reserved bits which are preset to 1 */
|
|
dr6 &= ~DR6_RESERVED;
|
|
|
|
/*
|
|
* The SDM says "The processor clears the BTF flag when it
|
|
* generates a debug exception." Clear TIF_BLOCKSTEP to keep
|
|
* TIF_BLOCKSTEP in sync with the hardware BTF flag.
|
|
*/
|
|
clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP);
|
|
|
|
if (unlikely(!user_mode(regs) && (dr6 & DR_STEP) &&
|
|
is_sysenter_singlestep(regs))) {
|
|
dr6 &= ~DR_STEP;
|
|
if (!dr6)
|
|
goto exit;
|
|
/*
|
|
* else we might have gotten a single-step trap and hit a
|
|
* watchpoint at the same time, in which case we should fall
|
|
* through and handle the watchpoint.
|
|
*/
|
|
}
|
|
|
|
/*
|
|
* If dr6 has no reason to give us about the origin of this trap,
|
|
* then it's very likely the result of an icebp/int01 trap.
|
|
* User wants a sigtrap for that.
|
|
*/
|
|
if (!dr6 && user_mode(regs))
|
|
user_icebp = 1;
|
|
|
|
/* Store the virtualized DR6 value */
|
|
tsk->thread.debugreg6 = dr6;
|
|
|
|
#ifdef CONFIG_KPROBES
|
|
if (kprobe_debug_handler(regs))
|
|
goto exit;
|
|
#endif
|
|
|
|
if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code,
|
|
SIGTRAP) == NOTIFY_STOP)
|
|
goto exit;
|
|
|
|
/*
|
|
* Let others (NMI) know that the debug stack is in use
|
|
* as we may switch to the interrupt stack.
|
|
*/
|
|
debug_stack_usage_inc();
|
|
|
|
/* It's safe to allow irq's after DR6 has been saved */
|
|
cond_local_irq_enable(regs);
|
|
|
|
if (v8086_mode(regs)) {
|
|
handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code,
|
|
X86_TRAP_DB);
|
|
cond_local_irq_disable(regs);
|
|
debug_stack_usage_dec();
|
|
goto exit;
|
|
}
|
|
|
|
if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) {
|
|
/*
|
|
* Historical junk that used to handle SYSENTER single-stepping.
|
|
* This should be unreachable now. If we survive for a while
|
|
* without anyone hitting this warning, we'll turn this into
|
|
* an oops.
|
|
*/
|
|
tsk->thread.debugreg6 &= ~DR_STEP;
|
|
set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
|
|
regs->flags &= ~X86_EFLAGS_TF;
|
|
}
|
|
si_code = get_si_code(tsk->thread.debugreg6);
|
|
if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
|
|
send_sigtrap(regs, error_code, si_code);
|
|
cond_local_irq_disable(regs);
|
|
debug_stack_usage_dec();
|
|
|
|
exit:
|
|
ist_exit(regs);
|
|
}
|
|
NOKPROBE_SYMBOL(do_debug);
|
|
|
|
/*
|
|
* Note that we play around with the 'TS' bit in an attempt to get
|
|
* the correct behaviour even in the presence of the asynchronous
|
|
* IRQ13 behaviour
|
|
*/
|
|
static void math_error(struct pt_regs *regs, int error_code, int trapnr)
|
|
{
|
|
struct task_struct *task = current;
|
|
struct fpu *fpu = &task->thread.fpu;
|
|
int si_code;
|
|
char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
|
|
"simd exception";
|
|
|
|
cond_local_irq_enable(regs);
|
|
|
|
if (!user_mode(regs)) {
|
|
if (fixup_exception(regs, trapnr, error_code, 0))
|
|
return;
|
|
|
|
task->thread.error_code = error_code;
|
|
task->thread.trap_nr = trapnr;
|
|
|
|
if (notify_die(DIE_TRAP, str, regs, error_code,
|
|
trapnr, SIGFPE) != NOTIFY_STOP)
|
|
die(str, regs, error_code);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Save the info for the exception handler and clear the error.
|
|
*/
|
|
fpu__save(fpu);
|
|
|
|
task->thread.trap_nr = trapnr;
|
|
task->thread.error_code = error_code;
|
|
|
|
si_code = fpu__exception_code(fpu, trapnr);
|
|
/* Retry when we get spurious exceptions: */
|
|
if (!si_code)
|
|
return;
|
|
|
|
force_sig_fault(SIGFPE, si_code,
|
|
(void __user *)uprobe_get_trap_addr(regs));
|
|
}
|
|
|
|
dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code)
|
|
{
|
|
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
|
|
math_error(regs, error_code, X86_TRAP_MF);
|
|
}
|
|
|
|
dotraplinkage void
|
|
do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
|
|
{
|
|
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
|
|
math_error(regs, error_code, X86_TRAP_XF);
|
|
}
|
|
|
|
dotraplinkage void
|
|
do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
|
|
{
|
|
cond_local_irq_enable(regs);
|
|
}
|
|
|
|
dotraplinkage void
|
|
do_device_not_available(struct pt_regs *regs, long error_code)
|
|
{
|
|
unsigned long cr0 = read_cr0();
|
|
|
|
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
|
|
|
|
#ifdef CONFIG_MATH_EMULATION
|
|
if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
|
|
struct math_emu_info info = { };
|
|
|
|
cond_local_irq_enable(regs);
|
|
|
|
info.regs = regs;
|
|
math_emulate(&info);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
/* This should not happen. */
|
|
if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
|
|
/* Try to fix it up and carry on. */
|
|
write_cr0(cr0 & ~X86_CR0_TS);
|
|
} else {
|
|
/*
|
|
* Something terrible happened, and we're better off trying
|
|
* to kill the task than getting stuck in a never-ending
|
|
* loop of #NM faults.
|
|
*/
|
|
die("unexpected #NM exception", regs, error_code);
|
|
}
|
|
}
|
|
NOKPROBE_SYMBOL(do_device_not_available);
|
|
|
|
#ifdef CONFIG_X86_32
|
|
dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code)
|
|
{
|
|
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
|
|
local_irq_enable();
|
|
|
|
if (notify_die(DIE_TRAP, "iret exception", regs, error_code,
|
|
X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
|
|
do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code,
|
|
ILL_BADSTK, (void __user *)NULL);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
void __init trap_init(void)
|
|
{
|
|
/* Init cpu_entry_area before IST entries are set up */
|
|
setup_cpu_entry_areas();
|
|
|
|
idt_setup_traps();
|
|
|
|
/*
|
|
* Set the IDT descriptor to a fixed read-only location, so that the
|
|
* "sidt" instruction will not leak the location of the kernel, and
|
|
* to defend the IDT against arbitrary memory write vulnerabilities.
|
|
* It will be reloaded in cpu_init() */
|
|
cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
|
|
PAGE_KERNEL_RO);
|
|
idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
|
|
|
|
/*
|
|
* Should be a barrier for any external CPU state:
|
|
*/
|
|
cpu_init();
|
|
|
|
idt_setup_ist_traps();
|
|
|
|
x86_init.irqs.trap_init();
|
|
|
|
idt_setup_debugidt_traps();
|
|
}
|