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b9a801dfa5
Add an MFD driver for Intel Merrifield Basin Cove PMIC. Firmware on the platforms which are using Basin Cove PMIC is "smarter" than on the rest supported by vanilla kernel. It handles first level of interrupt itself, while others do it on OS level. The driver is done in the same way as the rest of Intel PMIC MFD drivers in the kernel to support the initial design. The design allows to use one driver among few PMICs without knowing implementation details of the each hardware version or generation. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
81 lines
2.2 KiB
C
81 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Header file for Intel Merrifield Basin Cove PMIC
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*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_SOC_PMIC_MRFLD_H__
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#define __INTEL_SOC_PMIC_MRFLD_H__
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#include <linux/bits.h>
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#define BCOVE_ID 0x00
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#define BCOVE_ID_MINREV0 GENMASK(2, 0)
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#define BCOVE_ID_MAJREV0 GENMASK(5, 3)
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#define BCOVE_ID_VENDID0 GENMASK(7, 6)
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#define BCOVE_MINOR(x) (unsigned int)(((x) & BCOVE_ID_MINREV0) >> 0)
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#define BCOVE_MAJOR(x) (unsigned int)(((x) & BCOVE_ID_MAJREV0) >> 3)
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#define BCOVE_VENDOR(x) (unsigned int)(((x) & BCOVE_ID_VENDID0) >> 6)
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#define BCOVE_IRQLVL1 0x01
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#define BCOVE_PBIRQ 0x02
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#define BCOVE_TMUIRQ 0x03
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#define BCOVE_THRMIRQ 0x04
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#define BCOVE_BCUIRQ 0x05
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#define BCOVE_ADCIRQ 0x06
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#define BCOVE_CHGRIRQ0 0x07
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#define BCOVE_CHGRIRQ1 0x08
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#define BCOVE_GPIOIRQ 0x09
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#define BCOVE_CRITIRQ 0x0B
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#define BCOVE_MIRQLVL1 0x0C
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#define BCOVE_MPBIRQ 0x0D
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#define BCOVE_MTMUIRQ 0x0E
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#define BCOVE_MTHRMIRQ 0x0F
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#define BCOVE_MBCUIRQ 0x10
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#define BCOVE_MADCIRQ 0x11
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#define BCOVE_MCHGRIRQ0 0x12
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#define BCOVE_MCHGRIRQ1 0x13
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#define BCOVE_MGPIOIRQ 0x14
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#define BCOVE_MCRITIRQ 0x16
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#define BCOVE_SCHGRIRQ0 0x4E
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#define BCOVE_SCHGRIRQ1 0x4F
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/* Level 1 IRQs */
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#define BCOVE_LVL1_PWRBTN BIT(0) /* power button */
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#define BCOVE_LVL1_TMU BIT(1) /* time management unit */
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#define BCOVE_LVL1_THRM BIT(2) /* thermal */
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#define BCOVE_LVL1_BCU BIT(3) /* burst control unit */
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#define BCOVE_LVL1_ADC BIT(4) /* ADC */
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#define BCOVE_LVL1_CHGR BIT(5) /* charger */
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#define BCOVE_LVL1_GPIO BIT(6) /* GPIO */
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#define BCOVE_LVL1_CRIT BIT(7) /* critical event */
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/* Level 2 IRQs: power button */
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#define BCOVE_PBIRQ_PBTN BIT(0)
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#define BCOVE_PBIRQ_UBTN BIT(1)
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/* Level 2 IRQs: ADC */
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#define BCOVE_ADCIRQ_BATTEMP BIT(2)
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#define BCOVE_ADCIRQ_SYSTEMP BIT(3)
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#define BCOVE_ADCIRQ_BATTID BIT(4)
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#define BCOVE_ADCIRQ_VIBATT BIT(5)
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#define BCOVE_ADCIRQ_CCTICK BIT(7)
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/* Level 2 IRQs: charger */
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#define BCOVE_CHGRIRQ_BAT0ALRT BIT(4)
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#define BCOVE_CHGRIRQ_BAT1ALRT BIT(5)
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#define BCOVE_CHGRIRQ_BATCRIT BIT(6)
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#define BCOVE_CHGRIRQ_VBUSDET BIT(0)
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#define BCOVE_CHGRIRQ_DCDET BIT(1)
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#define BCOVE_CHGRIRQ_BATTDET BIT(2)
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#define BCOVE_CHGRIRQ_USBIDDET BIT(3)
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#endif /* __INTEL_SOC_PMIC_MRFLD_H__ */
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