mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-22 18:41:06 +00:00
9b76d71fa8
In addition to We have a handful of new features for 5.14:
* Support for transparent huge pages.
* Support for generic PCI resources mapping.
* Support for the mem= kernel parameter.
* Support for KFENCE.
* A handful of fixes to avoid W+X mappings in the kernel.
* Support for VMAP_STACK based overflow detection.
* An optimized copy_{to,from}_user.
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Merge tag 'riscv-for-linus-5.14-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
"We have a handful of new features for 5.14:
- Support for transparent huge pages.
- Support for generic PCI resources mapping.
- Support for the mem= kernel parameter.
- Support for KFENCE.
- A handful of fixes to avoid W+X mappings in the kernel.
- Support for VMAP_STACK based overflow detection.
- An optimized copy_{to,from}_user"
* tag 'riscv-for-linus-5.14-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (37 commits)
riscv: xip: Fix duplicate included asm/pgtable.h
riscv: Fix PTDUMP output now BPF region moved back to module region
riscv: __asm_copy_to-from_user: Optimize unaligned memory access and pipeline stall
riscv: add VMAP_STACK overflow detection
riscv: ptrace: add argn syntax
riscv: mm: fix build errors caused by mk_pmd()
riscv: Introduce structure that group all variables regarding kernel mapping
riscv: Map the kernel with correct permissions the first time
riscv: Introduce set_kernel_memory helper
riscv: Enable KFENCE for riscv64
RISC-V: Use asm-generic for {in,out}{bwlq}
riscv: add ASID-based tlbflushing methods
riscv: pass the mm_struct to __sbi_tlb_flush_range
riscv: Add mem kernel parameter support
riscv: Simplify xip and !xip kernel address conversion macros
riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED
riscv: Only initialize swiotlb when necessary
riscv: fix typo in init.c
riscv: Cleanup unused functions
riscv: mm: Use better bitmap_zalloc()
...
145 lines
2.8 KiB
ArmAsm
145 lines
2.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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* Copyright (C) 2020 Vitaly Wool, Konsulko AB
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*/
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#include <asm/pgtable.h>
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#define LOAD_OFFSET KERNEL_LINK_ADDR
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/* No __ro_after_init data in the .rodata section - which will always be ro */
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#define RO_AFTER_INIT_DATA
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#include <asm/vmlinux.lds.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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jiffies = jiffies_64;
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SECTIONS
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{
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/* Beginning of code and text segment */
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. = LOAD_OFFSET;
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_xiprom = .;
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_start = .;
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HEAD_TEXT_SECTION
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INIT_TEXT_SECTION(PAGE_SIZE)
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/* we have to discard exit text and such at runtime, not link time */
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.exit.text :
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{
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EXIT_TEXT
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}
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.text : {
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_text = .;
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_stext = .;
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TEXT_TEXT
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SCHED_TEXT
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CPUIDLE_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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ENTRY_TEXT
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IRQENTRY_TEXT
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SOFTIRQENTRY_TEXT
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*(.fixup)
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_etext = .;
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}
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RO_DATA(L1_CACHE_BYTES)
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.srodata : {
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*(.srodata*)
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}
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.init.rodata : {
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INIT_SETUP(16)
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INIT_CALLS
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CON_INITCALL
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INIT_RAM_FS
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}
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_exiprom = .; /* End of XIP ROM area */
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/*
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* From this point, stuff is considered writable and will be copied to RAM
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*/
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__data_loc = ALIGN(16); /* location in file */
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. = LOAD_OFFSET + XIP_OFFSET; /* location in memory */
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_sdata = .; /* Start of data section */
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_data = .;
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RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
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_edata = .;
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__start_ro_after_init = .;
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.data.ro_after_init : AT(ADDR(.data.ro_after_init) - LOAD_OFFSET) {
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*(.data..ro_after_init)
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}
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__end_ro_after_init = .;
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. = ALIGN(PAGE_SIZE);
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__init_begin = .;
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.init.data : {
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INIT_DATA
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}
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.exit.data : {
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EXIT_DATA
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}
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. = ALIGN(8);
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__soc_early_init_table : {
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__soc_early_init_table_start = .;
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KEEP(*(__soc_early_init_table))
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__soc_early_init_table_end = .;
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}
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__soc_builtin_dtb_table : {
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__soc_builtin_dtb_table_start = .;
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KEEP(*(__soc_builtin_dtb_table))
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__soc_builtin_dtb_table_end = .;
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}
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PERCPU_SECTION(L1_CACHE_BYTES)
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. = ALIGN(8);
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.alternative : {
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__alt_start = .;
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*(.alternative)
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__alt_end = .;
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}
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__init_end = .;
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. = ALIGN(16);
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.xip.traps : {
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__xip_traps_start = .;
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*(.xip.traps)
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__xip_traps_end = .;
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}
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. = ALIGN(PAGE_SIZE);
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.sdata : {
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__global_pointer$ = . + 0x800;
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*(.sdata*)
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*(.sbss*)
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}
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BSS_SECTION(PAGE_SIZE, PAGE_SIZE, 0)
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EXCEPTION_TABLE(0x10)
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.rel.dyn : AT(ADDR(.rel.dyn) - LOAD_OFFSET) {
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*(.rel.dyn*)
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}
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/*
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* End of copied data. We need a dummy section to get its LMA.
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* Also located before final ALIGN() as trailing padding is not stored
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* in the resulting binary file and useless to copy.
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*/
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.data.endmark : AT(ADDR(.data.endmark) - LOAD_OFFSET) { }
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_edata_loc = LOADADDR(.data.endmark);
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. = ALIGN(PAGE_SIZE);
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_end = .;
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STABS_DEBUG
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DWARF_DEBUG
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DISCARDS
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}
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