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30ad29bb48
Currently, code of Loongson-2/3 is under loongson directory and code of Loongson-1 is under loongson1 directory. Besides, there are Kconfig options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is very ugly and confusing. Since Loongson-2/3 are both 64-bit general- purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names and Kconfig symbols from loongson/loongson1 to loongson64/loongson32. [ralf@linux-mips.org: Resolve a number of simple conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
198 lines
5.2 KiB
C
198 lines
5.2 KiB
C
/*
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* Copyright (c) 2011 Zhao Zhang <zhzhl555@gmail.com>
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*
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* Derived from driver/rtc/rtc-au1xxx.c
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/rtc.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <loongson1.h>
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#define LS1X_RTC_REG_OFFSET (LS1X_RTC_BASE + 0x20)
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#define LS1X_RTC_REGS(x) \
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((void __iomem *)KSEG1ADDR(LS1X_RTC_REG_OFFSET + (x)))
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/*RTC programmable counters 0 and 1*/
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#define SYS_COUNTER_CNTRL (LS1X_RTC_REGS(0x20))
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#define SYS_CNTRL_ERS (1 << 23)
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#define SYS_CNTRL_RTS (1 << 20)
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#define SYS_CNTRL_RM2 (1 << 19)
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#define SYS_CNTRL_RM1 (1 << 18)
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#define SYS_CNTRL_RM0 (1 << 17)
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#define SYS_CNTRL_RS (1 << 16)
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#define SYS_CNTRL_BP (1 << 14)
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#define SYS_CNTRL_REN (1 << 13)
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#define SYS_CNTRL_BRT (1 << 12)
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#define SYS_CNTRL_TEN (1 << 11)
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#define SYS_CNTRL_BTT (1 << 10)
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#define SYS_CNTRL_E0 (1 << 8)
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#define SYS_CNTRL_ETS (1 << 7)
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#define SYS_CNTRL_32S (1 << 5)
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#define SYS_CNTRL_TTS (1 << 4)
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#define SYS_CNTRL_TM2 (1 << 3)
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#define SYS_CNTRL_TM1 (1 << 2)
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#define SYS_CNTRL_TM0 (1 << 1)
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#define SYS_CNTRL_TS (1 << 0)
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/* Programmable Counter 0 Registers */
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#define SYS_TOYTRIM (LS1X_RTC_REGS(0))
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#define SYS_TOYWRITE0 (LS1X_RTC_REGS(4))
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#define SYS_TOYWRITE1 (LS1X_RTC_REGS(8))
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#define SYS_TOYREAD0 (LS1X_RTC_REGS(0xC))
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#define SYS_TOYREAD1 (LS1X_RTC_REGS(0x10))
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#define SYS_TOYMATCH0 (LS1X_RTC_REGS(0x14))
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#define SYS_TOYMATCH1 (LS1X_RTC_REGS(0x18))
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#define SYS_TOYMATCH2 (LS1X_RTC_REGS(0x1C))
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/* Programmable Counter 1 Registers */
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#define SYS_RTCTRIM (LS1X_RTC_REGS(0x40))
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#define SYS_RTCWRITE0 (LS1X_RTC_REGS(0x44))
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#define SYS_RTCREAD0 (LS1X_RTC_REGS(0x48))
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#define SYS_RTCMATCH0 (LS1X_RTC_REGS(0x4C))
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#define SYS_RTCMATCH1 (LS1X_RTC_REGS(0x50))
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#define SYS_RTCMATCH2 (LS1X_RTC_REGS(0x54))
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#define LS1X_SEC_OFFSET (4)
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#define LS1X_MIN_OFFSET (10)
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#define LS1X_HOUR_OFFSET (16)
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#define LS1X_DAY_OFFSET (21)
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#define LS1X_MONTH_OFFSET (26)
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#define LS1X_SEC_MASK (0x3f)
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#define LS1X_MIN_MASK (0x3f)
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#define LS1X_HOUR_MASK (0x1f)
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#define LS1X_DAY_MASK (0x1f)
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#define LS1X_MONTH_MASK (0x3f)
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#define LS1X_YEAR_MASK (0xffffffff)
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#define ls1x_get_sec(t) (((t) >> LS1X_SEC_OFFSET) & LS1X_SEC_MASK)
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#define ls1x_get_min(t) (((t) >> LS1X_MIN_OFFSET) & LS1X_MIN_MASK)
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#define ls1x_get_hour(t) (((t) >> LS1X_HOUR_OFFSET) & LS1X_HOUR_MASK)
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#define ls1x_get_day(t) (((t) >> LS1X_DAY_OFFSET) & LS1X_DAY_MASK)
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#define ls1x_get_month(t) (((t) >> LS1X_MONTH_OFFSET) & LS1X_MONTH_MASK)
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#define RTC_CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
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static int ls1x_rtc_read_time(struct device *dev, struct rtc_time *rtm)
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{
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unsigned long v, t;
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v = readl(SYS_TOYREAD0);
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t = readl(SYS_TOYREAD1);
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memset(rtm, 0, sizeof(struct rtc_time));
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t = mktime((t & LS1X_YEAR_MASK), ls1x_get_month(v),
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ls1x_get_day(v), ls1x_get_hour(v),
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ls1x_get_min(v), ls1x_get_sec(v));
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rtc_time_to_tm(t, rtm);
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return rtc_valid_tm(rtm);
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}
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static int ls1x_rtc_set_time(struct device *dev, struct rtc_time *rtm)
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{
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unsigned long v, t, c;
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int ret = -ETIMEDOUT;
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v = ((rtm->tm_mon + 1) << LS1X_MONTH_OFFSET)
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| (rtm->tm_mday << LS1X_DAY_OFFSET)
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| (rtm->tm_hour << LS1X_HOUR_OFFSET)
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| (rtm->tm_min << LS1X_MIN_OFFSET)
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| (rtm->tm_sec << LS1X_SEC_OFFSET);
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writel(v, SYS_TOYWRITE0);
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c = 0x10000;
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/* add timeout check counter, for more safe */
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while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c)
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usleep_range(1000, 3000);
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if (!c) {
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dev_err(dev, "set time timeout!\n");
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goto err;
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}
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t = rtm->tm_year + 1900;
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writel(t, SYS_TOYWRITE1);
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c = 0x10000;
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while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c)
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usleep_range(1000, 3000);
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if (!c) {
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dev_err(dev, "set time timeout!\n");
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goto err;
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}
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return 0;
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err:
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return ret;
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}
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static struct rtc_class_ops ls1x_rtc_ops = {
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.read_time = ls1x_rtc_read_time,
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.set_time = ls1x_rtc_set_time,
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};
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static int ls1x_rtc_probe(struct platform_device *pdev)
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{
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struct rtc_device *rtcdev;
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unsigned long v;
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int ret;
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v = readl(SYS_COUNTER_CNTRL);
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if (!(v & RTC_CNTR_OK)) {
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dev_err(&pdev->dev, "rtc counters not working\n");
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ret = -ENODEV;
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goto err;
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}
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ret = -ETIMEDOUT;
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/* set to 1 HZ if needed */
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if (readl(SYS_TOYTRIM) != 32767) {
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v = 0x100000;
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while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS) && --v)
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usleep_range(1000, 3000);
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if (!v) {
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dev_err(&pdev->dev, "time out\n");
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goto err;
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}
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writel(32767, SYS_TOYTRIM);
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}
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/* this loop coundn't be endless */
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while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS)
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usleep_range(1000, 3000);
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rtcdev = devm_rtc_device_register(&pdev->dev, "ls1x-rtc",
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&ls1x_rtc_ops , THIS_MODULE);
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if (IS_ERR(rtcdev)) {
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ret = PTR_ERR(rtcdev);
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goto err;
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}
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platform_set_drvdata(pdev, rtcdev);
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return 0;
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err:
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return ret;
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}
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static struct platform_driver ls1x_rtc_driver = {
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.driver = {
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.name = "ls1x-rtc",
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},
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.probe = ls1x_rtc_probe,
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};
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module_platform_driver(ls1x_rtc_driver);
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MODULE_AUTHOR("zhao zhang <zhzhl555@gmail.com>");
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MODULE_LICENSE("GPL");
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