Christoph Hellwig 8bf90f320d riscv: implement remote sfence.i using IPIs ... The RISC-V ISA only supports flushing the instruction cache for the local CPU core. Currently we always offload the remote TLB flushing to the SBI, which then issues an IPI under the hoods. But with M-mode we do not have an SBI so we have to do it ourselves. IPI to the other nodes using the existing kernel helpers instead if we have native clint support and thus can IPI directly from the kernel. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: cleaned up code comment] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-11-13 13:24:21 -08:00
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asm	riscv: implement remote sfence.i using IPIs	2019-11-13 13:24:21 -08:00
uapi/asm	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00