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According to USB4 retimer specification, the process of firmware update sequence requires issuing a SET_INBOUND_SBTX port operation that later shall be followed by UNSET_INBOUND_SBTX port operation. This last step is not currently issued by the driver but it is necessary to make sure the retimers are put back to passthrough mode even during enumeration. If this step is missing the link may not come up properly after soft-reboot for example. For this reason issue UNSET_INBOUND_SBTX after SET_INBOUND_SBTX for enumeration and also when the NVM upgrade is run. Reported-by: Christian Schaubschläger <christian.schaubschlaeger@gmx.at> Link: https://lore.kernel.org/linux-usb/b556f5ed-5ee8-9990-9910-afd60db93310@gmx.at/ Cc: stable@vger.kernel.org Signed-off-by: Gil Fine <gil.fine@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
94 lines
3.7 KiB
C
94 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* USB4 port sideband registers found on routers and retimers
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*
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* Copyright (C) 2020, Intel Corporation
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* Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
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* Rajmohan Mani <rajmohan.mani@intel.com>
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*/
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#ifndef _SB_REGS
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#define _SB_REGS
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#define USB4_SB_VENDOR_ID 0x00
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#define USB4_SB_PRODUCT_ID 0x01
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#define USB4_SB_OPCODE 0x08
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enum usb4_sb_opcode {
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USB4_SB_OPCODE_ERR = 0x20525245, /* "ERR " */
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USB4_SB_OPCODE_ONS = 0x444d4321, /* "!CMD" */
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USB4_SB_OPCODE_ROUTER_OFFLINE = 0x4e45534c, /* "LSEN" */
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USB4_SB_OPCODE_ENUMERATE_RETIMERS = 0x4d554e45, /* "ENUM" */
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USB4_SB_OPCODE_SET_INBOUND_SBTX = 0x5055534c, /* "LSUP" */
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USB4_SB_OPCODE_UNSET_INBOUND_SBTX = 0x50555355, /* "USUP" */
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USB4_SB_OPCODE_QUERY_LAST_RETIMER = 0x5453414c, /* "LAST" */
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USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE = 0x53534e47, /* "GNSS" */
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USB4_SB_OPCODE_NVM_SET_OFFSET = 0x53504f42, /* "BOPS" */
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USB4_SB_OPCODE_NVM_BLOCK_WRITE = 0x574b4c42, /* "BLKW" */
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USB4_SB_OPCODE_NVM_AUTH_WRITE = 0x48545541, /* "AUTH" */
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USB4_SB_OPCODE_NVM_READ = 0x52524641, /* "AFRR" */
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USB4_SB_OPCODE_READ_LANE_MARGINING_CAP = 0x50434452, /* "RDCP" */
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USB4_SB_OPCODE_RUN_HW_LANE_MARGINING = 0x474d4852, /* "RHMG" */
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USB4_SB_OPCODE_RUN_SW_LANE_MARGINING = 0x474d5352, /* "RSMG" */
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USB4_SB_OPCODE_READ_SW_MARGIN_ERR = 0x57534452, /* "RDSW" */
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};
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#define USB4_SB_METADATA 0x09
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#define USB4_SB_METADATA_NVM_AUTH_WRITE_MASK GENMASK(5, 0)
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#define USB4_SB_DATA 0x12
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/* USB4_SB_OPCODE_READ_LANE_MARGINING_CAP */
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#define USB4_MARGIN_CAP_0_MODES_HW BIT(0)
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#define USB4_MARGIN_CAP_0_MODES_SW BIT(1)
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#define USB4_MARGIN_CAP_0_2_LANES BIT(2)
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#define USB4_MARGIN_CAP_0_VOLTAGE_INDP_MASK GENMASK(4, 3)
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#define USB4_MARGIN_CAP_0_VOLTAGE_INDP_SHIFT 3
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#define USB4_MARGIN_CAP_0_VOLTAGE_MIN 0x0
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#define USB4_MARGIN_CAP_0_VOLTAGE_HL 0x1
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#define USB4_MARGIN_CAP_0_VOLTAGE_BOTH 0x2
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#define USB4_MARGIN_CAP_0_TIME BIT(5)
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#define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_MASK GENMASK(12, 6)
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#define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_SHIFT 6
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#define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_MASK GENMASK(18, 13)
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#define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_SHIFT 13
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#define USB4_MARGIN_CAP_1_TIME_DESTR BIT(8)
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#define USB4_MARGIN_CAP_1_TIME_INDP_MASK GENMASK(10, 9)
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#define USB4_MARGIN_CAP_1_TIME_INDP_SHIFT 9
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#define USB4_MARGIN_CAP_1_TIME_MIN 0x0
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#define USB4_MARGIN_CAP_1_TIME_LR 0x1
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#define USB4_MARGIN_CAP_1_TIME_BOTH 0x2
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#define USB4_MARGIN_CAP_1_TIME_STEPS_MASK GENMASK(15, 11)
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#define USB4_MARGIN_CAP_1_TIME_STEPS_SHIFT 11
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#define USB4_MARGIN_CAP_1_TIME_OFFSET_MASK GENMASK(20, 16)
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#define USB4_MARGIN_CAP_1_TIME_OFFSET_SHIFT 16
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#define USB4_MARGIN_CAP_1_MIN_BER_MASK GENMASK(25, 21)
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#define USB4_MARGIN_CAP_1_MIN_BER_SHIFT 21
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#define USB4_MARGIN_CAP_1_MAX_BER_MASK GENMASK(30, 26)
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#define USB4_MARGIN_CAP_1_MAX_BER_SHIFT 26
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#define USB4_MARGIN_CAP_1_MAX_BER_SHIFT 26
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/* USB4_SB_OPCODE_RUN_HW_LANE_MARGINING */
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#define USB4_MARGIN_HW_TIME BIT(3)
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#define USB4_MARGIN_HW_RH BIT(4)
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#define USB4_MARGIN_HW_BER_MASK GENMASK(9, 5)
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#define USB4_MARGIN_HW_BER_SHIFT 5
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/* Applicable to all margin values */
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#define USB4_MARGIN_HW_RES_1_MARGIN_MASK GENMASK(6, 0)
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#define USB4_MARGIN_HW_RES_1_EXCEEDS BIT(7)
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/* Different lane margin shifts */
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#define USB4_MARGIN_HW_RES_1_L0_LL_MARGIN_SHIFT 8
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#define USB4_MARGIN_HW_RES_1_L1_RH_MARGIN_SHIFT 16
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#define USB4_MARGIN_HW_RES_1_L1_LL_MARGIN_SHIFT 24
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/* USB4_SB_OPCODE_RUN_SW_LANE_MARGINING */
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#define USB4_MARGIN_SW_TIME BIT(3)
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#define USB4_MARGIN_SW_RH BIT(4)
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#define USB4_MARGIN_SW_COUNTER_MASK GENMASK(14, 13)
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#define USB4_MARGIN_SW_COUNTER_SHIFT 13
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#define USB4_MARGIN_SW_COUNTER_NOP 0x0
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#define USB4_MARGIN_SW_COUNTER_CLEAR 0x1
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#define USB4_MARGIN_SW_COUNTER_START 0x2
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#define USB4_MARGIN_SW_COUNTER_STOP 0x3
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#endif
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