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![Changbin Du](/assets/img/avatar_default.png)
GVTg has introduced the context status notifier to schedule the GVTg
workload. At that time, the notifier is bound to GVTg context only,
so GVTg is not aware of host workloads.
Now we are going to improve GVTg's guest workload scheduler policy,
and add Guc emulation support for new Gen graphics. Both these two
features require acknowledgment for all contexts running on hardware.
(But will not alter host workload.) So here try to make some change.
The change is simple:
1. Move the context status notifier head from i915_gem_context to
intel_engine_cs. Which means there is a notifier head per engine
instead of per context. Execlist driver still call notifier for
each context sched-in/out events of current engine.
2. At GVTg side, it binds a notifier_block for each physical engine
at GVTg initialization period. Then GVTg can hear all context
status events.
In this patch, GVTg do nothing for host context event, but later
will add a function there. But in any case, the notifier callback is
a noop if this is no active vGPU.
Since intel_gvt_init() is called at early initialization stage and
require the status notifier head has been initiated, I initiate it in
intel_engine_setup().
v2: remove a redundant newline. (chris)
Fixes: 3c7ba6359d
("drm/i915: Introduce execlist context status change notification")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100232
Signed-off-by: Changbin Du <changbin.du@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20170313024711.28591-1-changbin.du@intel.com
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
679 lines
23 KiB
C
679 lines
23 KiB
C
#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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#include <linux/hashtable.h>
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#include "i915_gem_batch_pool.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_selftest.h"
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#define I915_CMD_HASH_ORDER 9
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/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
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* but keeps the logic simple. Indeed, the whole purpose of this macro is just
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* to give some inclination as to some of the magic values used in the various
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* workarounds!
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*/
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#define CACHELINE_BYTES 64
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#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
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/*
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* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
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* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
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* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
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*
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* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
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* cacheline, the Head Pointer must not be greater than the Tail
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* Pointer."
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*/
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#define I915_RING_FREE_SPACE 64
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struct intel_hw_status_page {
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struct i915_vma *vma;
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u32 *page_addr;
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u32 ggtt_offset;
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};
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#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
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#define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
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#define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
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#define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
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#define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
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#define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
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#define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
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#define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
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#define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
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#define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
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#define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
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#define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
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/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
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* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
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*/
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#define gen8_semaphore_seqno_size sizeof(uint64_t)
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#define GEN8_SEMAPHORE_OFFSET(__from, __to) \
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(((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
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#define GEN8_SIGNAL_OFFSET(__ring, to) \
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(dev_priv->semaphore->node.start + \
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GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
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#define GEN8_WAIT_OFFSET(__ring, from) \
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(dev_priv->semaphore->node.start + \
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GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
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enum intel_engine_hangcheck_action {
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ENGINE_IDLE = 0,
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ENGINE_WAIT,
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ENGINE_ACTIVE_SEQNO,
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ENGINE_ACTIVE_HEAD,
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ENGINE_ACTIVE_SUBUNITS,
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ENGINE_WAIT_KICK,
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ENGINE_DEAD,
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};
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static inline const char *
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hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
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{
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switch (a) {
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case ENGINE_IDLE:
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return "idle";
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case ENGINE_WAIT:
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return "wait";
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case ENGINE_ACTIVE_SEQNO:
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return "active seqno";
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case ENGINE_ACTIVE_HEAD:
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return "active head";
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case ENGINE_ACTIVE_SUBUNITS:
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return "active subunits";
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case ENGINE_WAIT_KICK:
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return "wait kick";
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case ENGINE_DEAD:
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return "dead";
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}
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return "unknown";
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}
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#define I915_MAX_SLICES 3
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#define I915_MAX_SUBSLICES 3
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#define instdone_slice_mask(dev_priv__) \
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(INTEL_GEN(dev_priv__) == 7 ? \
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1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
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#define instdone_subslice_mask(dev_priv__) \
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(INTEL_GEN(dev_priv__) == 7 ? \
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1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
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#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
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for ((slice__) = 0, (subslice__) = 0; \
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(slice__) < I915_MAX_SLICES; \
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(subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
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(slice__) += ((subslice__) == 0)) \
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for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
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(BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
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struct intel_instdone {
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u32 instdone;
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/* The following exist only in the RCS engine */
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u32 slice_common;
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u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
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u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
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};
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struct intel_engine_hangcheck {
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u64 acthd;
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u32 seqno;
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enum intel_engine_hangcheck_action action;
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unsigned long action_timestamp;
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int deadlock;
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struct intel_instdone instdone;
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bool stalled;
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};
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struct intel_ring {
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struct i915_vma *vma;
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void *vaddr;
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struct intel_engine_cs *engine;
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struct list_head request_list;
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u32 head;
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u32 tail;
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int space;
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int size;
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int effective_size;
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/** We track the position of the requests in the ring buffer, and
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* when each is retired we increment last_retired_head as the GPU
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* must have finished processing the request and so we know we
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* can advance the ringbuffer up to that position.
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*
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* last_retired_head is set to -1 after the value is consumed so
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* we can detect new retirements.
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*/
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u32 last_retired_head;
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};
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struct i915_gem_context;
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struct drm_i915_reg_table;
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/*
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* we use a single page to load ctx workarounds so all of these
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* values are referred in terms of dwords
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*
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* struct i915_wa_ctx_bb:
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* offset: specifies batch starting position, also helpful in case
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* if we want to have multiple batches at different offsets based on
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* some criteria. It is not a requirement at the moment but provides
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* an option for future use.
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* size: size of the batch in DWORDS
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*/
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struct i915_ctx_workarounds {
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struct i915_wa_ctx_bb {
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u32 offset;
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u32 size;
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} indirect_ctx, per_ctx;
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struct i915_vma *vma;
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};
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struct drm_i915_gem_request;
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struct intel_render_state;
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/*
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* Engine IDs definitions.
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* Keep instances of the same type engine together.
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*/
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enum intel_engine_id {
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RCS = 0,
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BCS,
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VCS,
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VCS2,
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#define _VCS(n) (VCS + (n))
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VECS
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};
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struct intel_engine_cs {
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struct drm_i915_private *i915;
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const char *name;
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enum intel_engine_id id;
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unsigned int exec_id;
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unsigned int hw_id;
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unsigned int guc_id;
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u32 mmio_base;
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unsigned int irq_shift;
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struct intel_ring *buffer;
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struct intel_timeline *timeline;
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struct intel_render_state *render_state;
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atomic_t irq_count;
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unsigned long irq_posted;
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#define ENGINE_IRQ_BREADCRUMB 0
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#define ENGINE_IRQ_EXECLIST 1
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/* Rather than have every client wait upon all user interrupts,
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* with the herd waking after every interrupt and each doing the
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* heavyweight seqno dance, we delegate the task (of being the
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* bottom-half of the user interrupt) to the first client. After
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* every interrupt, we wake up one client, who does the heavyweight
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* coherent seqno read and either goes back to sleep (if incomplete),
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* or wakes up all the completed clients in parallel, before then
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* transferring the bottom-half status to the next client in the queue.
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*
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* Compared to walking the entire list of waiters in a single dedicated
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* bottom-half, we reduce the latency of the first waiter by avoiding
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* a context switch, but incur additional coherent seqno reads when
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* following the chain of request breadcrumbs. Since it is most likely
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* that we have a single client waiting on each seqno, then reducing
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* the overhead of waking that client is much preferred.
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*/
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struct intel_breadcrumbs {
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spinlock_t irq_lock; /* protects irq_*; irqsafe */
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struct intel_wait *irq_wait; /* oldest waiter by retirement */
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spinlock_t rb_lock; /* protects the rb and wraps irq_lock */
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struct rb_root waiters; /* sorted by retirement, priority */
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struct rb_root signals; /* sorted by retirement */
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struct task_struct *signaler; /* used for fence signalling */
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struct drm_i915_gem_request __rcu *first_signal;
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struct timer_list fake_irq; /* used after a missed interrupt */
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struct timer_list hangcheck; /* detect missed interrupts */
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unsigned int hangcheck_interrupts;
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bool irq_armed : 1;
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bool irq_enabled : 1;
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I915_SELFTEST_DECLARE(bool mock : 1);
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} breadcrumbs;
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/*
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* A pool of objects to use as shadow copies of client batch buffers
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* when the command parser is enabled. Prevents the client from
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* modifying the batch contents after software parsing.
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*/
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struct i915_gem_batch_pool batch_pool;
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struct intel_hw_status_page status_page;
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struct i915_ctx_workarounds wa_ctx;
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struct i915_vma *scratch;
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u32 irq_keep_mask; /* always keep these interrupts */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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void (*irq_enable)(struct intel_engine_cs *engine);
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void (*irq_disable)(struct intel_engine_cs *engine);
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int (*init_hw)(struct intel_engine_cs *engine);
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void (*reset_hw)(struct intel_engine_cs *engine,
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struct drm_i915_gem_request *req);
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int (*context_pin)(struct intel_engine_cs *engine,
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struct i915_gem_context *ctx);
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void (*context_unpin)(struct intel_engine_cs *engine,
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struct i915_gem_context *ctx);
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int (*request_alloc)(struct drm_i915_gem_request *req);
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int (*init_context)(struct drm_i915_gem_request *req);
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int (*emit_flush)(struct drm_i915_gem_request *request,
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u32 mode);
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#define EMIT_INVALIDATE BIT(0)
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#define EMIT_FLUSH BIT(1)
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#define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
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int (*emit_bb_start)(struct drm_i915_gem_request *req,
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u64 offset, u32 length,
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unsigned int dispatch_flags);
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#define I915_DISPATCH_SECURE BIT(0)
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#define I915_DISPATCH_PINNED BIT(1)
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#define I915_DISPATCH_RS BIT(2)
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void (*emit_breadcrumb)(struct drm_i915_gem_request *req,
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u32 *cs);
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int emit_breadcrumb_sz;
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/* Pass the request to the hardware queue (e.g. directly into
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* the legacy ringbuffer or to the end of an execlist).
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*
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* This is called from an atomic context with irqs disabled; must
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* be irq safe.
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*/
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void (*submit_request)(struct drm_i915_gem_request *req);
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/* Call when the priority on a request has changed and it and its
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* dependencies may need rescheduling. Note the request itself may
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* not be ready to run!
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*
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* Called under the struct_mutex.
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*/
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void (*schedule)(struct drm_i915_gem_request *request,
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int priority);
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/* Some chipsets are not quite as coherent as advertised and need
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* an expensive kick to force a true read of the up-to-date seqno.
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* However, the up-to-date seqno is not always required and the last
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* seen value is good enough. Note that the seqno will always be
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* monotonic, even if not coherent.
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*/
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void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
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void (*cleanup)(struct intel_engine_cs *engine);
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/* GEN8 signal/wait table - never trust comments!
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* signal to signal to signal to signal to signal to
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
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* ie. transpose of g(x, y)
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*
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* sync from sync from sync from sync from sync from
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
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* ie. transpose of f(x, y)
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*/
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struct {
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union {
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#define GEN6_SEMAPHORE_LAST VECS_HW
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#define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
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#define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
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struct {
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/* our mbox written by others */
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u32 wait[GEN6_NUM_SEMAPHORES];
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/* mboxes this ring signals to */
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i915_reg_t signal[GEN6_NUM_SEMAPHORES];
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} mbox;
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u64 signal_ggtt[I915_NUM_ENGINES];
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};
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/* AKA wait() */
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int (*sync_to)(struct drm_i915_gem_request *req,
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struct drm_i915_gem_request *signal);
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u32 *(*signal)(struct drm_i915_gem_request *req, u32 *cs);
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} semaphore;
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/* Execlists */
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struct tasklet_struct irq_tasklet;
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struct execlist_port {
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struct drm_i915_gem_request *request;
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unsigned int count;
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GEM_DEBUG_DECL(u32 context_id);
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} execlist_port[2];
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struct rb_root execlist_queue;
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struct rb_node *execlist_first;
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unsigned int fw_domains;
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/* Contexts are pinned whilst they are active on the GPU. The last
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* context executed remains active whilst the GPU is idle - the
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* switch away and write to the context object only occurs on the
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* next execution. Contexts are only unpinned on retirement of the
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* following request ensuring that we can always write to the object
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* on the context switch even after idling. Across suspend, we switch
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* to the kernel context and trash it as the save may not happen
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* before the hardware is powered down.
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*/
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struct i915_gem_context *last_retired_context;
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/* We track the current MI_SET_CONTEXT in order to eliminate
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* redudant context switches. This presumes that requests are not
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* reordered! Or when they are the tracking is updated along with
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* the emission of individual requests into the legacy command
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* stream (ring).
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*/
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struct i915_gem_context *legacy_active_context;
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/* status_notifier: list of callbacks for context-switch changes */
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struct atomic_notifier_head context_status_notifier;
|
|
|
|
struct intel_engine_hangcheck hangcheck;
|
|
|
|
bool needs_cmd_parser;
|
|
|
|
/*
|
|
* Table of commands the command parser needs to know about
|
|
* for this engine.
|
|
*/
|
|
DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
|
|
|
|
/*
|
|
* Table of registers allowed in commands that read/write registers.
|
|
*/
|
|
const struct drm_i915_reg_table *reg_tables;
|
|
int reg_table_count;
|
|
|
|
/*
|
|
* Returns the bitmask for the length field of the specified command.
|
|
* Return 0 for an unrecognized/invalid command.
|
|
*
|
|
* If the command parser finds an entry for a command in the engine's
|
|
* cmd_tables, it gets the command's length based on the table entry.
|
|
* If not, it calls this function to determine the per-engine length
|
|
* field encoding for the command (i.e. different opcode ranges use
|
|
* certain bits to encode the command length in the header).
|
|
*/
|
|
u32 (*get_cmd_length_mask)(u32 cmd_header);
|
|
};
|
|
|
|
static inline unsigned
|
|
intel_engine_flag(const struct intel_engine_cs *engine)
|
|
{
|
|
return 1 << engine->id;
|
|
}
|
|
|
|
static inline void
|
|
intel_flush_status_page(struct intel_engine_cs *engine, int reg)
|
|
{
|
|
mb();
|
|
clflush(&engine->status_page.page_addr[reg]);
|
|
mb();
|
|
}
|
|
|
|
static inline u32
|
|
intel_read_status_page(struct intel_engine_cs *engine, int reg)
|
|
{
|
|
/* Ensure that the compiler doesn't optimize away the load. */
|
|
return READ_ONCE(engine->status_page.page_addr[reg]);
|
|
}
|
|
|
|
static inline void
|
|
intel_write_status_page(struct intel_engine_cs *engine,
|
|
int reg, u32 value)
|
|
{
|
|
mb();
|
|
clflush(&engine->status_page.page_addr[reg]);
|
|
engine->status_page.page_addr[reg] = value;
|
|
clflush(&engine->status_page.page_addr[reg]);
|
|
mb();
|
|
}
|
|
|
|
/*
|
|
* Reads a dword out of the status page, which is written to from the command
|
|
* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
|
|
* MI_STORE_DATA_IMM.
|
|
*
|
|
* The following dwords have a reserved meaning:
|
|
* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
|
|
* 0x04: ring 0 head pointer
|
|
* 0x05: ring 1 head pointer (915-class)
|
|
* 0x06: ring 2 head pointer (915-class)
|
|
* 0x10-0x1b: Context status DWords (GM45)
|
|
* 0x1f: Last written status offset. (GM45)
|
|
* 0x20-0x2f: Reserved (Gen6+)
|
|
*
|
|
* The area from dword 0x30 to 0x3ff is available for driver usage.
|
|
*/
|
|
#define I915_GEM_HWS_INDEX 0x30
|
|
#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
|
|
#define I915_GEM_HWS_SCRATCH_INDEX 0x40
|
|
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
|
|
|
|
struct intel_ring *
|
|
intel_engine_create_ring(struct intel_engine_cs *engine, int size);
|
|
int intel_ring_pin(struct intel_ring *ring, unsigned int offset_bias);
|
|
void intel_ring_unpin(struct intel_ring *ring);
|
|
void intel_ring_free(struct intel_ring *ring);
|
|
|
|
void intel_engine_stop(struct intel_engine_cs *engine);
|
|
void intel_engine_cleanup(struct intel_engine_cs *engine);
|
|
|
|
void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);
|
|
|
|
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
|
|
|
|
u32 __must_check *intel_ring_begin(struct drm_i915_gem_request *req, int n);
|
|
|
|
static inline void
|
|
intel_ring_advance(struct drm_i915_gem_request *req, u32 *cs)
|
|
{
|
|
/* Dummy function.
|
|
*
|
|
* This serves as a placeholder in the code so that the reader
|
|
* can compare against the preceding intel_ring_begin() and
|
|
* check that the number of dwords emitted matches the space
|
|
* reserved for the command packet (i.e. the value passed to
|
|
* intel_ring_begin()).
|
|
*/
|
|
GEM_BUG_ON((req->ring->vaddr + req->ring->tail) != cs);
|
|
}
|
|
|
|
static inline u32
|
|
intel_ring_offset(struct drm_i915_gem_request *req, void *addr)
|
|
{
|
|
/* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
|
|
u32 offset = addr - req->ring->vaddr;
|
|
GEM_BUG_ON(offset > req->ring->size);
|
|
return offset & (req->ring->size - 1);
|
|
}
|
|
|
|
void intel_ring_update_space(struct intel_ring *ring);
|
|
|
|
void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
|
|
|
|
void intel_engine_setup_common(struct intel_engine_cs *engine);
|
|
int intel_engine_init_common(struct intel_engine_cs *engine);
|
|
int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
|
|
void intel_engine_cleanup_common(struct intel_engine_cs *engine);
|
|
|
|
int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
|
|
int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
|
|
int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine);
|
|
int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
|
|
int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
|
|
|
|
u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
|
|
u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine);
|
|
|
|
static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
|
|
{
|
|
return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
|
|
}
|
|
|
|
static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)
|
|
{
|
|
/* We are only peeking at the tail of the submit queue (and not the
|
|
* queue itself) in order to gain a hint as to the current active
|
|
* state of the engine. Callers are not expected to be taking
|
|
* engine->timeline->lock, nor are they expected to be concerned
|
|
* wtih serialising this hint with anything, so document it as
|
|
* a hint and nothing more.
|
|
*/
|
|
return READ_ONCE(engine->timeline->seqno);
|
|
}
|
|
|
|
int init_workarounds_ring(struct intel_engine_cs *engine);
|
|
int intel_ring_workarounds_emit(struct drm_i915_gem_request *req);
|
|
|
|
void intel_engine_get_instdone(struct intel_engine_cs *engine,
|
|
struct intel_instdone *instdone);
|
|
|
|
/*
|
|
* Arbitrary size for largest possible 'add request' sequence. The code paths
|
|
* are complex and variable. Empirical measurement shows that the worst case
|
|
* is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
|
|
* we need to allocate double the largest single packet within that emission
|
|
* to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
|
|
*/
|
|
#define MIN_SPACE_FOR_ADD_REQUEST 336
|
|
|
|
static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
|
|
{
|
|
return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
|
|
}
|
|
|
|
/* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
|
|
int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
|
|
|
|
static inline void intel_wait_init(struct intel_wait *wait,
|
|
struct drm_i915_gem_request *rq)
|
|
{
|
|
wait->tsk = current;
|
|
wait->request = rq;
|
|
}
|
|
|
|
static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 seqno)
|
|
{
|
|
wait->tsk = current;
|
|
wait->seqno = seqno;
|
|
}
|
|
|
|
static inline bool intel_wait_has_seqno(const struct intel_wait *wait)
|
|
{
|
|
return wait->seqno;
|
|
}
|
|
|
|
static inline bool
|
|
intel_wait_update_seqno(struct intel_wait *wait, u32 seqno)
|
|
{
|
|
wait->seqno = seqno;
|
|
return intel_wait_has_seqno(wait);
|
|
}
|
|
|
|
static inline bool
|
|
intel_wait_update_request(struct intel_wait *wait,
|
|
const struct drm_i915_gem_request *rq)
|
|
{
|
|
return intel_wait_update_seqno(wait, i915_gem_request_global_seqno(rq));
|
|
}
|
|
|
|
static inline bool
|
|
intel_wait_check_seqno(const struct intel_wait *wait, u32 seqno)
|
|
{
|
|
return wait->seqno == seqno;
|
|
}
|
|
|
|
static inline bool
|
|
intel_wait_check_request(const struct intel_wait *wait,
|
|
const struct drm_i915_gem_request *rq)
|
|
{
|
|
return intel_wait_check_seqno(wait, i915_gem_request_global_seqno(rq));
|
|
}
|
|
|
|
static inline bool intel_wait_complete(const struct intel_wait *wait)
|
|
{
|
|
return RB_EMPTY_NODE(&wait->node);
|
|
}
|
|
|
|
bool intel_engine_add_wait(struct intel_engine_cs *engine,
|
|
struct intel_wait *wait);
|
|
void intel_engine_remove_wait(struct intel_engine_cs *engine,
|
|
struct intel_wait *wait);
|
|
void intel_engine_enable_signaling(struct drm_i915_gem_request *request);
|
|
void intel_engine_cancel_signaling(struct drm_i915_gem_request *request);
|
|
|
|
static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
|
|
{
|
|
return READ_ONCE(engine->breadcrumbs.irq_wait);
|
|
}
|
|
|
|
unsigned int intel_engine_wakeup(struct intel_engine_cs *engine);
|
|
#define ENGINE_WAKEUP_WAITER BIT(0)
|
|
#define ENGINE_WAKEUP_ASLEEP BIT(1)
|
|
|
|
void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
|
|
void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
|
|
|
|
void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
|
|
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
|
|
bool intel_breadcrumbs_busy(struct intel_engine_cs *engine);
|
|
|
|
static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
|
|
{
|
|
memset(batch, 0, 6 * sizeof(u32));
|
|
|
|
batch[0] = GFX_OP_PIPE_CONTROL(6);
|
|
batch[1] = flags;
|
|
batch[2] = offset;
|
|
|
|
return batch + 6;
|
|
}
|
|
|
|
bool intel_engine_is_idle(struct intel_engine_cs *engine);
|
|
bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
|
|
|
|
#endif /* _INTEL_RINGBUFFER_H_ */
|