Paolo Bonzini 9167ab7993 KVM: vmx, svm: always run with EFER.NXE=1 when shadow paging is active ... VMX already does so if the host has SMEP, in order to support the combination of CR0.WP=1 and CR4.SMEP=1. However, it is perfectly safe to always do so, and in fact VMX already ends up running with EFER.NXE=1 on old processors that lack the "load EFER" controls, because it may help avoiding a slow MSR write. Removing all the conditionals simplifies the code. SVM does not have similar code, but it should since recent AMD processors do support SMEP. So this patch also makes the code for the two vendors more similar while fixing NPT=0, CR0.WP=1 and CR4.SMEP=1 on AMD processors. Cc: stable@vger.kernel.org Cc: Joerg Roedel <jroedel@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2019-10-31 12:13:44 +01:00
..
capabilities.h	KVM: x86: Add support for user wait instructions	2019-09-24 14:34:20 +02:00
evmcs.c	x86/kvm/nVMX: fix VMCLEAR when Enlightened VMCS is in use	2019-07-02 18:56:00 +02:00
evmcs.h	KVM/Hyper-V/VMX: Add direct tlb flush support	2019-09-24 13:37:14 +02:00
nested.c	KVM: nVMX: Don't leak L1 MMIO regions to L2	2019-10-22 19:04:40 +02:00
nested.h	KVM: nVMX: Don't leak L1 MMIO regions to L2	2019-10-22 19:04:40 +02:00
ops.h	KVM: VMX: Add error handling to VMREAD helper	2019-09-25 15:30:09 +02:00
pmu_intel.c	kvm: vmx: Limit guest PMCs to those supported on the host	2019-10-01 15:15:06 +02:00
vmcs.h	KVM: VMX: Leave preemption timer running when it's disabled	2019-06-18 17:10:46 +02:00
vmcs12.c
vmcs12.h	KVM/arm updates for 5.3	2019-07-11 15:14:16 +02:00
vmcs_shadow_fields.h	KVM: nVMX: shadow pin based execution controls	2019-06-18 17:10:50 +02:00
vmenter.S	KVM: VMX: Fix and tweak the comments for VM-Enter	2019-08-22 10:09:27 +02:00
vmx.c	KVM: vmx, svm: always run with EFER.NXE=1 when shadow paging is active	2019-10-31 12:13:44 +01:00
vmx.h	KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL	2019-09-24 14:34:36 +02:00