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![Krzysztof Kozlowski](/assets/img/avatar_default.png)
The 'pm_data', 'exynos_release_ret_regs', 'exynos3250_release_ret_regs' and 'exynos5420_release_ret_regs' are not exported nor used outside of suspend.c file. Make them static. This fixes following sparse warnings: arch/arm/mach-exynos/suspend.c:83:23: warning: symbol 'pm_data' was not declared. Should it be static? arch/arm/mach-exynos/suspend.c:106:14: warning: symbol 'exynos_release_ret_regs' was not declared. Should it be static? arch/arm/mach-exynos/suspend.c:117:14: warning: symbol 'exynos5420_release_ret_regs' was not declared. Should it be static? Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
640 lines
15 KiB
C
640 lines
15 KiB
C
/*
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* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - Suspend support
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*
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* Based on arch/arm/mach-s3c2410/pm.c
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/syscore_ops.h>
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#include <linux/cpu_pm.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/err.h>
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#include <linux/regulator/machine.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/firmware.h>
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#include <asm/mcpm.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <plat/pm-common.h>
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#include <plat/regs-srom.h>
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#include "common.h"
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#include "regs-pmu.h"
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#include "exynos-pmu.h"
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#define S5P_CHECK_SLEEP 0x00000BAD
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#define REG_TABLE_END (-1U)
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#define EXYNOS5420_CPU_STATE 0x28
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/**
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* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
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* @hwirq: Hardware IRQ signal of the GIC
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* @mask: Mask in PMU wake-up mask register
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*/
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struct exynos_wkup_irq {
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unsigned int hwirq;
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u32 mask;
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};
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static struct sleep_save exynos_core_save[] = {
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/* SROM side */
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SAVE_ITEM(S5P_SROM_BW),
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SAVE_ITEM(S5P_SROM_BC0),
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SAVE_ITEM(S5P_SROM_BC1),
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SAVE_ITEM(S5P_SROM_BC2),
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SAVE_ITEM(S5P_SROM_BC3),
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};
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struct exynos_pm_data {
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const struct exynos_wkup_irq *wkup_irq;
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struct sleep_save *extra_save;
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int num_extra_save;
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unsigned int wake_disable_mask;
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unsigned int *release_ret_regs;
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void (*pm_prepare)(void);
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void (*pm_resume_prepare)(void);
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void (*pm_resume)(void);
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int (*pm_suspend)(void);
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int (*cpu_suspend)(unsigned long);
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};
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static struct exynos_pm_data *pm_data;
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static int exynos5420_cpu_state;
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static unsigned int exynos_pmu_spare3;
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/*
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* GIC wake-up support
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*/
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static u32 exynos_irqwake_intmask = 0xffffffff;
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static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
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{ 73, BIT(1) }, /* RTC alarm */
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{ 74, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
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{ 76, BIT(1) }, /* RTC alarm */
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{ 77, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
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{ 75, BIT(1) }, /* RTC alarm */
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{ 76, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static unsigned int exynos_release_ret_regs[] = {
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S5P_PAD_RET_MAUDIO_OPTION,
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S5P_PAD_RET_GPIO_OPTION,
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S5P_PAD_RET_UART_OPTION,
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S5P_PAD_RET_MMCA_OPTION,
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S5P_PAD_RET_MMCB_OPTION,
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S5P_PAD_RET_EBIA_OPTION,
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S5P_PAD_RET_EBIB_OPTION,
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REG_TABLE_END,
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};
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static unsigned int exynos3250_release_ret_regs[] = {
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S5P_PAD_RET_MAUDIO_OPTION,
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S5P_PAD_RET_GPIO_OPTION,
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S5P_PAD_RET_UART_OPTION,
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S5P_PAD_RET_MMCA_OPTION,
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S5P_PAD_RET_MMCB_OPTION,
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S5P_PAD_RET_EBIA_OPTION,
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S5P_PAD_RET_EBIB_OPTION,
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S5P_PAD_RET_MMC2_OPTION,
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S5P_PAD_RET_SPI_OPTION,
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REG_TABLE_END,
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};
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static unsigned int exynos5420_release_ret_regs[] = {
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EXYNOS_PAD_RET_DRAM_OPTION,
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EXYNOS_PAD_RET_MAUDIO_OPTION,
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EXYNOS_PAD_RET_JTAG_OPTION,
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EXYNOS5420_PAD_RET_GPIO_OPTION,
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EXYNOS5420_PAD_RET_UART_OPTION,
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EXYNOS5420_PAD_RET_MMCA_OPTION,
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EXYNOS5420_PAD_RET_MMCB_OPTION,
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EXYNOS5420_PAD_RET_MMCC_OPTION,
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EXYNOS5420_PAD_RET_HSI_OPTION,
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EXYNOS_PAD_RET_EBIA_OPTION,
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EXYNOS_PAD_RET_EBIB_OPTION,
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EXYNOS5420_PAD_RET_SPI_OPTION,
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EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
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REG_TABLE_END,
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};
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static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
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{
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const struct exynos_wkup_irq *wkup_irq;
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if (!pm_data->wkup_irq)
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return -ENOENT;
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wkup_irq = pm_data->wkup_irq;
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while (wkup_irq->mask) {
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if (wkup_irq->hwirq == data->hwirq) {
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if (!state)
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exynos_irqwake_intmask |= wkup_irq->mask;
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else
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exynos_irqwake_intmask &= ~wkup_irq->mask;
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return 0;
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}
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++wkup_irq;
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}
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return -ENOENT;
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}
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static int exynos_cpu_do_idle(void)
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{
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/* issue the standby signal into the pm unit. */
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cpu_do_idle();
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pr_info("Failed to suspend the system\n");
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return 1; /* Aborting suspend */
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}
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static void exynos_flush_cache_all(void)
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{
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flush_cache_all();
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outer_flush_all();
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}
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static int exynos_cpu_suspend(unsigned long arg)
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{
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exynos_flush_cache_all();
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return exynos_cpu_do_idle();
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}
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static int exynos3250_cpu_suspend(unsigned long arg)
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{
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flush_cache_all();
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return exynos_cpu_do_idle();
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}
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static int exynos5420_cpu_suspend(unsigned long arg)
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{
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/* MCPM works with HW CPU identifiers */
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unsigned int mpidr = read_cpuid_mpidr();
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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__raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
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mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
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/*
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* Residency value passed to mcpm_cpu_suspend back-end
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* has to be given clear semantics. Set to 0 as a
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* temporary value.
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*/
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mcpm_cpu_suspend(0);
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}
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pr_info("Failed to suspend the system\n");
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/* return value != 0 means failure */
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return 1;
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}
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static void exynos_pm_set_wakeup_mask(void)
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{
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/* Set wake-up mask registers */
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pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
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pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
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}
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static void exynos_pm_enter_sleep_mode(void)
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{
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/* Set value of power down register for sleep mode */
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exynos_sys_powerdown_conf(SYS_SLEEP);
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pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
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}
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static void exynos_pm_prepare(void)
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{
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (pm_data->extra_save)
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s3c_pm_do_save(pm_data->extra_save,
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pm_data->num_extra_save);
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos3250_pm_prepare(void)
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{
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unsigned int tmp;
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
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tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
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pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos5420_pm_prepare(void)
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{
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unsigned int tmp;
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
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/*
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* The cpu state needs to be saved and restored so that the
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* secondary CPUs will enter low power start. Though the U-Boot
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* is setting the cpu state with low power flag, the kernel
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* needs to restore it back in case, the primary cpu fails to
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* suspend for any reason.
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*/
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exynos5420_cpu_state = __raw_readl(sysram_base_addr +
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EXYNOS5420_CPU_STATE);
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
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tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
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tmp &= ~EXYNOS5_USE_RETENTION;
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pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
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tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
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tmp |= EXYNOS5420_UFS;
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pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
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tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
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tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
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pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
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tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
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tmp |= EXYNOS5420_EMULATION;
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pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
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tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
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tmp |= EXYNOS5420_EMULATION;
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pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
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}
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static int exynos_pm_suspend(void)
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{
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exynos_pm_central_suspend();
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/* Setting SEQ_OPTION register */
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pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
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S5P_CENTRAL_SEQ_OPTION);
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_save_register();
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return 0;
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}
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static int exynos5420_pm_suspend(void)
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{
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u32 this_cluster;
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exynos_pm_central_suspend();
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/* Setting SEQ_OPTION register */
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this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
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if (!this_cluster)
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pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
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S5P_CENTRAL_SEQ_OPTION);
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else
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pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
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S5P_CENTRAL_SEQ_OPTION);
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return 0;
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}
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static void exynos_pm_release_retention(void)
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{
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unsigned int i;
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for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
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pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
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pm_data->release_ret_regs[i]);
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}
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static void exynos_pm_resume(void)
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{
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u32 cpuid = read_cpuid_part();
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if (exynos_pm_central_resume())
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goto early_wakeup;
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/* For release retention */
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exynos_pm_release_retention();
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if (pm_data->extra_save)
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s3c_pm_do_restore_core(pm_data->extra_save,
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pm_data->num_extra_save);
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s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (cpuid == ARM_CPU_PART_CORTEX_A9)
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scu_enable(S5P_VA_SCU);
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if (call_firmware_op(resume) == -ENOSYS
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&& cpuid == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_restore_register();
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early_wakeup:
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/* Clear SLEEP mode set in INFORM1 */
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pmu_raw_writel(0x0, S5P_INFORM1);
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}
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static void exynos3250_pm_resume(void)
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{
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u32 cpuid = read_cpuid_part();
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if (exynos_pm_central_resume())
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goto early_wakeup;
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/* For release retention */
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exynos_pm_release_retention();
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pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
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if (call_firmware_op(resume) == -ENOSYS
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&& cpuid == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_restore_register();
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early_wakeup:
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/* Clear SLEEP mode set in INFORM1 */
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pmu_raw_writel(0x0, S5P_INFORM1);
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}
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static void exynos5420_prepare_pm_resume(void)
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{
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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WARN_ON(mcpm_cpu_powered_up());
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}
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static void exynos5420_pm_resume(void)
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{
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unsigned long tmp;
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/* Restore the CPU0 low power state register */
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tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
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pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
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EXYNOS5_ARM_CORE0_SYS_PWR_REG);
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/* Restore the sysram cpu state register */
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__raw_writel(exynos5420_cpu_state,
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sysram_base_addr + EXYNOS5420_CPU_STATE);
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pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
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S5P_CENTRAL_SEQ_OPTION);
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if (exynos_pm_central_resume())
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goto early_wakeup;
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/* For release retention */
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exynos_pm_release_retention();
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pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
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s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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early_wakeup:
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tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
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tmp &= ~EXYNOS5420_UFS;
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pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
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tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
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tmp &= ~EXYNOS5420_EMULATION;
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pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
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tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
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tmp &= ~EXYNOS5420_EMULATION;
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pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
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/* Clear SLEEP mode set in INFORM1 */
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pmu_raw_writel(0x0, S5P_INFORM1);
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}
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/*
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* Suspend Ops
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*/
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static int exynos_suspend_enter(suspend_state_t state)
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|
{
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int ret;
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|
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s3c_pm_debug_init();
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|
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S3C_PMDBG("%s: suspending the system...\n", __func__);
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|
|
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S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
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exynos_irqwake_intmask, exynos_get_eint_wake_mask());
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|
|
|
if (exynos_irqwake_intmask == -1U
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&& exynos_get_eint_wake_mask() == -1U) {
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pr_err("%s: No wake-up sources!\n", __func__);
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pr_err("%s: Aborting sleep\n", __func__);
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return -EINVAL;
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|
}
|
|
|
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s3c_pm_save_uarts();
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if (pm_data->pm_prepare)
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|
pm_data->pm_prepare();
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|
flush_cache_all();
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|
s3c_pm_check_store();
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|
|
|
ret = call_firmware_op(suspend);
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if (ret == -ENOSYS)
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ret = cpu_suspend(0, pm_data->cpu_suspend);
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|
if (ret)
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|
return ret;
|
|
|
|
if (pm_data->pm_resume_prepare)
|
|
pm_data->pm_resume_prepare();
|
|
s3c_pm_restore_uarts();
|
|
|
|
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
|
|
pmu_raw_readl(S5P_WAKEUP_STAT));
|
|
|
|
s3c_pm_check_restore();
|
|
|
|
S3C_PMDBG("%s: resuming the system...\n", __func__);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_suspend_prepare(void)
|
|
{
|
|
int ret;
|
|
|
|
/*
|
|
* REVISIT: It would be better if struct platform_suspend_ops
|
|
* .prepare handler get the suspend_state_t as a parameter to
|
|
* avoid hard-coding the suspend to mem state. It's safe to do
|
|
* it now only because the suspend_valid_only_mem function is
|
|
* used as the .valid callback used to check if a given state
|
|
* is supported by the platform anyways.
|
|
*/
|
|
ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
|
|
if (ret) {
|
|
pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
s3c_pm_check_prepare();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void exynos_suspend_finish(void)
|
|
{
|
|
int ret;
|
|
|
|
s3c_pm_check_cleanup();
|
|
|
|
ret = regulator_suspend_finish();
|
|
if (ret)
|
|
pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
|
|
}
|
|
|
|
static const struct platform_suspend_ops exynos_suspend_ops = {
|
|
.enter = exynos_suspend_enter,
|
|
.prepare = exynos_suspend_prepare,
|
|
.finish = exynos_suspend_finish,
|
|
.valid = suspend_valid_only_mem,
|
|
};
|
|
|
|
static const struct exynos_pm_data exynos3250_pm_data = {
|
|
.wkup_irq = exynos3250_wkup_irq,
|
|
.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
|
|
.release_ret_regs = exynos3250_release_ret_regs,
|
|
.pm_suspend = exynos_pm_suspend,
|
|
.pm_resume = exynos3250_pm_resume,
|
|
.pm_prepare = exynos3250_pm_prepare,
|
|
.cpu_suspend = exynos3250_cpu_suspend,
|
|
};
|
|
|
|
static const struct exynos_pm_data exynos4_pm_data = {
|
|
.wkup_irq = exynos4_wkup_irq,
|
|
.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
|
|
.release_ret_regs = exynos_release_ret_regs,
|
|
.pm_suspend = exynos_pm_suspend,
|
|
.pm_resume = exynos_pm_resume,
|
|
.pm_prepare = exynos_pm_prepare,
|
|
.cpu_suspend = exynos_cpu_suspend,
|
|
};
|
|
|
|
static const struct exynos_pm_data exynos5250_pm_data = {
|
|
.wkup_irq = exynos5250_wkup_irq,
|
|
.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
|
|
.release_ret_regs = exynos_release_ret_regs,
|
|
.pm_suspend = exynos_pm_suspend,
|
|
.pm_resume = exynos_pm_resume,
|
|
.pm_prepare = exynos_pm_prepare,
|
|
.cpu_suspend = exynos_cpu_suspend,
|
|
};
|
|
|
|
static struct exynos_pm_data exynos5420_pm_data = {
|
|
.wkup_irq = exynos5250_wkup_irq,
|
|
.wake_disable_mask = (0x7F << 7) | (0x1F << 1),
|
|
.release_ret_regs = exynos5420_release_ret_regs,
|
|
.pm_resume_prepare = exynos5420_prepare_pm_resume,
|
|
.pm_resume = exynos5420_pm_resume,
|
|
.pm_suspend = exynos5420_pm_suspend,
|
|
.pm_prepare = exynos5420_pm_prepare,
|
|
.cpu_suspend = exynos5420_cpu_suspend,
|
|
};
|
|
|
|
static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
|
|
{
|
|
.compatible = "samsung,exynos3250-pmu",
|
|
.data = &exynos3250_pm_data,
|
|
}, {
|
|
.compatible = "samsung,exynos4210-pmu",
|
|
.data = &exynos4_pm_data,
|
|
}, {
|
|
.compatible = "samsung,exynos4212-pmu",
|
|
.data = &exynos4_pm_data,
|
|
}, {
|
|
.compatible = "samsung,exynos4412-pmu",
|
|
.data = &exynos4_pm_data,
|
|
}, {
|
|
.compatible = "samsung,exynos5250-pmu",
|
|
.data = &exynos5250_pm_data,
|
|
}, {
|
|
.compatible = "samsung,exynos5420-pmu",
|
|
.data = &exynos5420_pm_data,
|
|
},
|
|
{ /*sentinel*/ },
|
|
};
|
|
|
|
static struct syscore_ops exynos_pm_syscore_ops;
|
|
|
|
void __init exynos_pm_init(void)
|
|
{
|
|
const struct of_device_id *match;
|
|
u32 tmp;
|
|
|
|
of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
|
|
if (!match) {
|
|
pr_err("Failed to find PMU node\n");
|
|
return;
|
|
}
|
|
pm_data = (struct exynos_pm_data *) match->data;
|
|
|
|
/* Platform-specific GIC callback */
|
|
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
|
|
|
|
/* All wakeup disable */
|
|
tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
|
|
tmp |= pm_data->wake_disable_mask;
|
|
pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
|
|
|
|
exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
|
|
exynos_pm_syscore_ops.resume = pm_data->pm_resume;
|
|
|
|
register_syscore_ops(&exynos_pm_syscore_ops);
|
|
suspend_set_ops(&exynos_suspend_ops);
|
|
}
|