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8c961bcca1
Currently the soc-cache code will always write to the device, meaning that we need the device to be powered and active at pretty much all times the system is active. Allowing cache only writes lays some groundwork for future enhancements to allow devices to be put into a full off state when the audio subsystem is idle. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
455 lines
9.4 KiB
C
455 lines
9.4 KiB
C
/*
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* soc-cache.c -- ASoC register cache helpers
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*
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* Copyright 2009 Wolfson Microelectronics PLC.
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*
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* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/i2c.h>
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#include <linux/spi/spi.h>
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#include <sound/soc.h>
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static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
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unsigned int reg)
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{
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u16 *cache = codec->reg_cache;
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if (reg >= codec->reg_cache_size)
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return -1;
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return cache[reg];
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}
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static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u16 *cache = codec->reg_cache;
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u8 data[2];
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int ret;
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BUG_ON(codec->volatile_register);
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data[0] = (reg << 4) | ((value >> 8) & 0x000f);
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data[1] = value & 0x00ff;
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if (reg < codec->reg_cache_size)
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cache[reg] = value;
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if (codec->cache_only)
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return 0;
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ret = codec->hw_write(codec->control_data, data, 2);
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if (ret == 2)
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return 0;
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if (ret < 0)
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return ret;
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else
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return -EIO;
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}
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#if defined(CONFIG_SPI_MASTER)
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static int snd_soc_4_12_spi_write(void *control_data, const char *data,
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int len)
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{
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struct spi_device *spi = control_data;
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struct spi_transfer t;
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struct spi_message m;
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u8 msg[2];
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if (len <= 0)
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return 0;
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msg[0] = data[1];
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msg[1] = data[0];
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spi_message_init(&m);
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memset(&t, 0, (sizeof t));
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t.tx_buf = &msg[0];
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t.len = len;
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spi_message_add_tail(&t, &m);
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spi_sync(spi, &m);
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return len;
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}
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#else
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#define snd_soc_4_12_spi_write NULL
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#endif
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static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
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unsigned int reg)
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{
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u16 *cache = codec->reg_cache;
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if (reg >= codec->reg_cache_size)
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return -1;
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return cache[reg];
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}
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static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u16 *cache = codec->reg_cache;
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u8 data[2];
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int ret;
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BUG_ON(codec->volatile_register);
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data[0] = (reg << 1) | ((value >> 8) & 0x0001);
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data[1] = value & 0x00ff;
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if (reg < codec->reg_cache_size)
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cache[reg] = value;
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if (codec->cache_only)
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return 0;
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ret = codec->hw_write(codec->control_data, data, 2);
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if (ret == 2)
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return 0;
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if (ret < 0)
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return ret;
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else
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return -EIO;
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}
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#if defined(CONFIG_SPI_MASTER)
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static int snd_soc_7_9_spi_write(void *control_data, const char *data,
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int len)
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{
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struct spi_device *spi = control_data;
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struct spi_transfer t;
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struct spi_message m;
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u8 msg[2];
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if (len <= 0)
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return 0;
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msg[0] = data[0];
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msg[1] = data[1];
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spi_message_init(&m);
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memset(&t, 0, (sizeof t));
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t.tx_buf = &msg[0];
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t.len = len;
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spi_message_add_tail(&t, &m);
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spi_sync(spi, &m);
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return len;
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}
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#else
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#define snd_soc_7_9_spi_write NULL
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#endif
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static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u8 *cache = codec->reg_cache;
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u8 data[2];
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BUG_ON(codec->volatile_register);
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data[0] = reg & 0xff;
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data[1] = value & 0xff;
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if (reg < codec->reg_cache_size)
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cache[reg] = value;
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if (codec->cache_only)
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return 0;
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if (codec->hw_write(codec->control_data, data, 2) == 2)
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return 0;
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else
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return -EIO;
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}
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static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
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unsigned int reg)
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{
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u8 *cache = codec->reg_cache;
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if (reg >= codec->reg_cache_size)
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return -1;
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return cache[reg];
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}
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static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u16 *reg_cache = codec->reg_cache;
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u8 data[3];
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data[0] = reg;
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data[1] = (value >> 8) & 0xff;
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data[2] = value & 0xff;
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if (!snd_soc_codec_volatile_register(codec, reg))
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reg_cache[reg] = value;
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if (codec->cache_only)
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return 0;
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if (codec->hw_write(codec->control_data, data, 3) == 3)
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return 0;
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else
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return -EIO;
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}
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static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
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unsigned int reg)
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{
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u16 *cache = codec->reg_cache;
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if (reg >= codec->reg_cache_size ||
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snd_soc_codec_volatile_register(codec, reg)) {
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if (codec->cache_only)
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return -EINVAL;
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return codec->hw_read(codec, reg);
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} else {
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return cache[reg];
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}
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}
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
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unsigned int r)
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{
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struct i2c_msg xfer[2];
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u8 reg = r;
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u16 data;
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int ret;
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struct i2c_client *client = codec->control_data;
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/* Write register */
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xfer[0].addr = client->addr;
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xfer[0].flags = 0;
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xfer[0].len = 1;
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xfer[0].buf = ®
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/* Read data */
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xfer[1].addr = client->addr;
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xfer[1].flags = I2C_M_RD;
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xfer[1].len = 2;
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xfer[1].buf = (u8 *)&data;
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ret = i2c_transfer(client->adapter, xfer, 2);
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if (ret != 2) {
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dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
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return 0;
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}
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return (data >> 8) | ((data & 0xff) << 8);
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}
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#else
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#define snd_soc_8_16_read_i2c NULL
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#endif
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
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unsigned int r)
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{
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struct i2c_msg xfer[2];
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u16 reg = r;
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u8 data;
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int ret;
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struct i2c_client *client = codec->control_data;
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/* Write register */
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xfer[0].addr = client->addr;
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xfer[0].flags = 0;
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xfer[0].len = 2;
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xfer[0].buf = (u8 *)®
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/* Read data */
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xfer[1].addr = client->addr;
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xfer[1].flags = I2C_M_RD;
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xfer[1].len = 1;
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xfer[1].buf = &data;
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ret = i2c_transfer(client->adapter, xfer, 2);
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if (ret != 2) {
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dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
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return 0;
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}
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return data;
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}
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#else
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#define snd_soc_16_8_read_i2c NULL
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#endif
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static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
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unsigned int reg)
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{
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u16 *cache = codec->reg_cache;
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reg &= 0xff;
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if (reg >= codec->reg_cache_size)
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return -1;
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return cache[reg];
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}
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static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u16 *cache = codec->reg_cache;
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u8 data[3];
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int ret;
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BUG_ON(codec->volatile_register);
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data[0] = (reg >> 8) & 0xff;
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data[1] = reg & 0xff;
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data[2] = value;
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reg &= 0xff;
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if (reg < codec->reg_cache_size)
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cache[reg] = value;
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if (codec->cache_only)
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return 0;
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ret = codec->hw_write(codec->control_data, data, 3);
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if (ret == 3)
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return 0;
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if (ret < 0)
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return ret;
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else
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return -EIO;
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}
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#if defined(CONFIG_SPI_MASTER)
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static int snd_soc_16_8_spi_write(void *control_data, const char *data,
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int len)
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{
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struct spi_device *spi = control_data;
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struct spi_transfer t;
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struct spi_message m;
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u8 msg[3];
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if (len <= 0)
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return 0;
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msg[0] = data[0];
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msg[1] = data[1];
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msg[2] = data[2];
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spi_message_init(&m);
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memset(&t, 0, (sizeof t));
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t.tx_buf = &msg[0];
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t.len = len;
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spi_message_add_tail(&t, &m);
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spi_sync(spi, &m);
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return len;
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}
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#else
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#define snd_soc_16_8_spi_write NULL
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#endif
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static struct {
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int addr_bits;
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int data_bits;
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int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
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int (*spi_write)(void *, const char *, int);
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unsigned int (*read)(struct snd_soc_codec *, unsigned int);
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unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
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} io_types[] = {
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{
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.addr_bits = 4, .data_bits = 12,
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.write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
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.spi_write = snd_soc_4_12_spi_write,
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},
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{
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.addr_bits = 7, .data_bits = 9,
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.write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
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.spi_write = snd_soc_7_9_spi_write,
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},
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{
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.addr_bits = 8, .data_bits = 8,
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.write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
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},
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{
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.addr_bits = 8, .data_bits = 16,
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.write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
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.i2c_read = snd_soc_8_16_read_i2c,
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},
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{
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.addr_bits = 16, .data_bits = 8,
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.write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
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.i2c_read = snd_soc_16_8_read_i2c,
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.spi_write = snd_soc_16_8_spi_write,
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},
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};
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/**
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* snd_soc_codec_set_cache_io: Set up standard I/O functions.
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*
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* @codec: CODEC to configure.
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* @type: Type of cache.
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* @addr_bits: Number of bits of register address data.
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* @data_bits: Number of bits of data per register.
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* @control: Control bus used.
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*
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* Register formats are frequently shared between many I2C and SPI
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* devices. In order to promote code reuse the ASoC core provides
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* some standard implementations of CODEC read and write operations
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* which can be set up using this function.
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*
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* The caller is responsible for allocating and initialising the
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* actual cache.
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*
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* Note that at present this code cannot be used by CODECs with
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* volatile registers.
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*/
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int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
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int addr_bits, int data_bits,
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enum snd_soc_control_type control)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(io_types); i++)
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if (io_types[i].addr_bits == addr_bits &&
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io_types[i].data_bits == data_bits)
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break;
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if (i == ARRAY_SIZE(io_types)) {
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printk(KERN_ERR
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"No I/O functions for %d bit address %d bit data\n",
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addr_bits, data_bits);
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return -EINVAL;
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}
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codec->write = io_types[i].write;
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codec->read = io_types[i].read;
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switch (control) {
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case SND_SOC_CUSTOM:
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break;
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case SND_SOC_I2C:
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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codec->hw_write = (hw_write_t)i2c_master_send;
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#endif
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if (io_types[i].i2c_read)
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codec->hw_read = io_types[i].i2c_read;
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break;
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case SND_SOC_SPI:
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if (io_types[i].spi_write)
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codec->hw_write = io_types[i].spi_write;
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break;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
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