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97e3d26b5e
Seth found that the CPU-entry-area; the piece of per-cpu data that is mapped into the userspace page-tables for kPTI is not subject to any randomization -- irrespective of kASLR settings. On x86_64 a whole P4D (512 GB) of virtual address space is reserved for this structure, which is plenty large enough to randomize things a little. As such, use a straight forward randomization scheme that avoids duplicates to spread the existing CPUs over the available space. [ bp: Fix le build. ] Reported-by: Seth Jenkins <sethjenkins@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de>
22 lines
623 B
C
22 lines
623 B
C
#ifndef _ASM_X86_PGTABLE_AREAS_H
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#define _ASM_X86_PGTABLE_AREAS_H
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#ifdef CONFIG_X86_32
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# include <asm/pgtable_32_areas.h>
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#endif
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/* Single page reserved for the readonly IDT mapping: */
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#define CPU_ENTRY_AREA_RO_IDT CPU_ENTRY_AREA_BASE
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#define CPU_ENTRY_AREA_PER_CPU (CPU_ENTRY_AREA_RO_IDT + PAGE_SIZE)
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#define CPU_ENTRY_AREA_RO_IDT_VADDR ((void *)CPU_ENTRY_AREA_RO_IDT)
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#ifdef CONFIG_X86_32
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#define CPU_ENTRY_AREA_MAP_SIZE (CPU_ENTRY_AREA_PER_CPU + \
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(CPU_ENTRY_AREA_SIZE * NR_CPUS) - \
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CPU_ENTRY_AREA_BASE)
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#else
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#define CPU_ENTRY_AREA_MAP_SIZE P4D_SIZE
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#endif
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#endif /* _ASM_X86_PGTABLE_AREAS_H */
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