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8bea147dfd
When there's phy initialization, we need to initiate a soft-reset
sequence. That's done through USBCMD.HCRST in the xHCI driver and its
initialization, However, the dwc3 driver may modify core configs before
the soft-reset. This may result in some connection instability. So,
ensure the phy is ready before the controller updates the GCTL.PRTCAPDIR
or other settings by issuing phy soft-reset.
Note that some host-mode configurations may not expose device registers
to initiate the controller soft-reset (via DCTL.CoreSftRst). So we reset
through GUSB3PIPECTL and GUSB2PHYCFG instead.
Cc: stable@vger.kernel.org
Fixes:
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.. | ||
core.c | ||
core.h | ||
debug.h | ||
debugfs.c | ||
drd.c | ||
dwc3-am62.c | ||
dwc3-exynos.c | ||
dwc3-haps.c | ||
dwc3-imx8mp.c | ||
dwc3-keystone.c | ||
dwc3-meson-g12a.c | ||
dwc3-octeon.c | ||
dwc3-of-simple.c | ||
dwc3-omap.c | ||
dwc3-pci.c | ||
dwc3-qcom.c | ||
dwc3-st.c | ||
dwc3-xilinx.c | ||
ep0.c | ||
gadget.c | ||
gadget.h | ||
host.c | ||
io.h | ||
Kconfig | ||
Makefile | ||
trace.c | ||
trace.h | ||
ulpi.c |