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User Accelerated Function Unit sub feature exposes the MMIO region of the AFU. After valid PR bitstream is programmed and the port is enabled, then this MMIO region could be accessed. This patch adds support to enumerate the AFU MMIO region and expose it to userspace via mmap file operation. Below interfaces are exposed to user: Sysfs interface: * /sys/class/fpga_region/<regionX>/<dfl-port.x>/afu_id Read-only. Indicate which PR bitstream is programmed to this AFU. Ioctl interfaces: * DFL_FPGA_PORT_GET_INFO Provide info to userspace on the number of supported region. Only UAFU region is supported now. * DFL_FPGA_PORT_GET_REGION_INFO Provide region information, including access permission, region size, offset from the start of device fd. Signed-off-by: Tim Whisonant <tim.whisonant@intel.com> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com> Signed-off-by: Shiva Rao <shiva.rao@intel.com> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
16 lines
661 B
Text
16 lines
661 B
Text
What: /sys/bus/platform/devices/dfl-port.0/id
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Date: June 2018
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KernelVersion: 4.19
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. It returns id of this port. One DFL FPGA device
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may have more than one port. Userspace could use this id to
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distinguish different ports under same FPGA device.
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What: /sys/bus/platform/devices/dfl-port.0/afu_id
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Date: June 2018
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KernelVersion: 4.19
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. User can program different PR bitstreams to FPGA
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Accelerator Function Unit (AFU) for different functions. It
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returns uuid which could be used to identify which PR bitstream
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is programmed in this AFU.
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